E.9. ARM946E-S processor registers

Table E.16 describes the ARM946E-S processor registers.

Table E.16. ARM946E-S processor registers

Register

Description

Access

Data

c0

ID register

Read-only

Read-only

Read-only

ID information

Cache configuration

Tightly coupled memory information

c1

Control register

Read/write

Configuration flags

c2

Cache control:

  • Data Cache Control

  • Instruction Cache Control

Read/write

DCache control flags

ICache control flags

c3

Bufferable Control

Read/write

DBuffer control flags

c5

Memory protection:

  • Data Cache Control

  • Instruction Cache Control

Read/write

DCache protection flags

ICache protection flags

c6

Memory Area Definition:

  • D memory region 0 to 7

  • I memory region 0 to 7

Read/write

Base, size, and enable

Base, size, and enable

c7

Cache operations:

  • Flush ICache

  • Flush ICache Entry by VA

  • Prefetch ICache Line

  • Flush DCache

  • Flush DCache Entry by VA

  • Clean DCache Entry by VA

  • Clean and Flush DCache entry by VA

  • Clean DCache Entry by index

  • Clean and Flush DCache entry by index

Write-only

SBZ

VA

Address

SBZ

VA

VA

VA

Index and segment

Index and segment

c9

Cache lockdown control:

  • Data Lockdown Control

  • Instruction Lockdown Control

  • Tightly coupled D memory control

  • Tightly coupled I memory control

Read/write

D-control value

I-control value

D-mem value

I-mem value

c13

Trace process ID register

Read/write

Trace process ID

c15

Test and Debug register

Read/write

Not supported by Multi-ICE

The encodings to read or write the registers are as follows:

c0

A data read with cp15_cache_selected = 0 accesses the ID register.

A data read with cp15_cache_selected = 1 accesses the Cache Configuration register.

A data read with cp15_cache_selected = 2 accesses the Tightly coupled memory information register.

c1

All data reads and writes occur as expected.

c2

A data read or write with cp15_cache_selected = 0 or cp15_cache_selected = 2 accesses the DCache bits.

A data read or write with cp15_cache_selected = 1 or cp15_cache_selected = 3 accesses the ICache bits.

c3

All data reads and writes occur as expected.

c5

A data read and write with cp15_cache_selected = 0 or cp15_cache_selected = 2 accesses the data protection access permissions.

A data read or write with cp15_cache_selected = 1 accesses the instruction protection access permissions.

c6

The data that is read or written is a memory area definition, and consists of a base address, a size value, and an enable flag. The memory area is specified by the cp15_current_memory_area variable.

Note

Unlike the ARM940T processor, there are not separate I and D versions of these registers.

c7

The function performed is determined by the value of the cp15_cache_selected variable, and by bits [2:0] of the data that is written, as shown in Table E.17.

Table E.17. ARM946E-S cp15 register 7 accesses

cp15_cache_selected

Bit 2

Bit 1

Bit 0

Purpose

0

0

0

0

Flush DCache

0

0

0

1

Flush DCache entry by VA

0

0

1

0

Clean DCache entry by VA

0

0

1

1

Clean and flush DCache entry by VA

0

1

0

0

Clean DCache Entry by index

0

1

0

1

Clean and flush DCache Entry by index

1

0

0

0

Flush ICache

1

0

0

1

Flush ICache entry by VA

1

0

1

0

Prefetch ICache line

The encoded function uses bits [31:3] of the data that is written, with bits [2:0] cleared. So if 0x80000002 is written to r7, and cp15_cache_selected = 1, then the instruction data at 0x80000000 is prefetched into the ICache.

c9

A data read or write with cp15_cache_selected = 0 accesses the data lockdown control.

A data read or write with cp15_cache_selected = 1 accesses the instruction lockdown control.

A data read or write with cp15_cache_selected = 2 accesses the tightly coupled data memory control.

A data read or write with cp15_cache_selected = 3 accesses the tightly coupled instruction memory control.

c13

All data reads and writes occur as expected.

Copyright © 1998-2002 ARM Limited. All rights reserved.ARM DUI 0048F
Non-Confidential