D.2.3. Performance counters

The ADS debuggers enable you to see the performance counters in the Intel XScale processor. However, the XScale processor does not automatically disable its performance counters when it enters debug state. Because using the debug monitor involves executing code, the performance counters increment when in debug state.

The Multi-ICE debug monitor disables the performance counters in debug state, and re-enables them on exit from debug state.

Because the debug handler cannot disable the counters immediately, some effect of debug state is seen on the counters whenever the processor enters and leaves debug state. For example, if a performance counter is configured to count the number of instructions executed, single stepping a single instruction counts 13 instructions executed, rather than the one expected. This is because 12 instructions are executed in entering debug state and disabling the counter, and later in re-enabling the counters and exiting debug state, as well as the single instruction stepped.

When starting execution from a breakpointed instruction, the debugger first single-steps past the breakpointed instruction, and then resumes execution of the program. Therefore when running from one breakpointed instruction to another breakpoint, the effect is doubled, and 26 additional instructions are recorded. When using semihosting this effect is seen for every semihosting SWI instruction executed.

Note

The figures given here are implementation-dependent, and might vary with different versions of Multi-ICE or XScale microarchitecture processor.

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