E.8. ARM940T processor registers

Table E.14 describes the ARM940T processor registers.

Table E.14. ARM940T processor registers

Register

Description

Access

Data

c0

ID register

Read-only

Read-only

ID information

Cache configuration[1]

c1

Control register

Read/write

Configuration flags

c2

Cache control:

  • Data Cache Control

  • Instruction Cache Control

Read/write

DCache control flags

ICache control flags

c3

Bufferable Control

Read/write

DBuffer control flags

c5

Memory protection:

  • Data Cache Control

  • Instruction Cache Control

Read/write

DCache protection flags

ICache protection flags

c6

Memory Area Definition:

  • D memory region 0 to 7

  • I memory region 0 to 7

Read/write

Base, size, and enable

Base, size, and enable

c7

Cache operations:

  • Flush ICache

  • Flush ICache Single Entry

  • Flush DCache

  • Flush DCache Single Entry

  • Clean DCache Entry

  • Prefetch ICache Line

  • Clean and Flush DCache entry

  • Drain Write Buffer

Write-only

SBZ

Index and segment

SBZ

Index and segment

Index and segment

Address

Index and segment

SBZ

c9

Cache lockdown control:

  • Data Lockdown Control

  • Instruction Lockdown Control

Read/write

D-control value

I-control value

c15

Test and Debug register

Read/write

Map I or D CAM flags

[1] Revision 1 onwards.

The encodings to read or write the registers are as follows:

c0

A data read with cp15_cache_selected = 0 accesses the ID register.

From revision 1 onwards, a data read with cp15_cache_selected = 1 accesses the Cache Configuration register.

c1

All data reads and writes occur as expected.

c2

A data read or write with cp15_cache_selected = 0 accesses the DCache bits.

A data read or write with cp15_cache_selected = 1 accesses the ICache bits.

c3

All data reads and writes occur as expected.

c5

A data read or write with cp15_cache_selected = 0 accesses the data protection access permissions.

A data read or write with cp15_cache_selected = 1 accesses the instruction protection access permissions.

c6

The data that is read or written is a memory area definition, and consists of a base address, a size value, and an enable flag. The memory area is specified by the cp15_current_memory_area variable, and the cp15_cache_selected variable selects between the D area (when 0) and the I area (when 1).

c7

The function performed is determined by the value of the cp15_cache_selected variable, and by bits [1:0] of the data that is written, as shown in Table E.15.

Table E.15. ARM940T cp15 register 7 accesses

cp15_cache_selected

Bit 1

Bit 0

Purpose

0

0

0

Flush DCache

0

0

1

Flush 1 entry DCache

0

1

0

Clean DCache entry

0

1

1

Clean and flush DCache entry

1

0

0

Flush ICache

1

0

1

Flush 1 entry ICache

1

1

0

Prefetch ICache cache line

1

1

1

Drain write buffer[1]

[1] Revision 1 onwards.

The encoded function uses bits [31:2] of the data that is written, with bits [1:0] cleared. So if 0x80000002 is written to r7, and cp15_cache_selected = 1, then the instruction data at 0x80000000 is prefetched into the ICache.

c8

A data read or write with cp15_cache_selected = 0 accesses the data lockdown control.

A data read or write with cp15_cache_selected = 1 accesses the instruction lockdown control.

c15

All data reads and writes occur as expected.

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