4.8.1. Enabling semihosting

When using the Multi-ICE DLL, semihosting is handled with either a real SWI exception handler, or by emulating a handler using breakpoints. You can modify this semihosting mechanism using the following debugger internal variables:


By default, this variable is set to 1 to enable breakpoint semihosting but you can set it to the following values:


Disables semihosting.


Enables start-stop semihosting, using breakpoint-based emulation of the SWI handler.


Enables DCC semihosting, using an exception handler that uses DCC to communicate with the host.

The S bit in vector_catch must not be used as an alternative to changing semihosting_enabled.


This variable controls the location of the breakpoint set by the Multi-ICE DLL to detect a semihosted SWI. It is set to 8 by default unless vector_address specifies high vectors are in use.

In ADW and ADU, you can access both of these variables by selecting Debugger Internals from the View menu. In AXD, debugger internal variables are accessed with dedicated windows. See the ADS Debuggers Guide for more information.

Start-stop semihosting

Start-stop, or standard, semihosting involves setting a breakpoint either on the SWI vector or somewhere else in cooperation with your own SWI handler, depending on the value of semihosting_vector.

When the breakpoint is hit Multi-ICE interprets it as a semihosting request:

  • the processor registers and memory are read as required to decode the request

  • the request is executed on the host

  • the return value is placed in register R0 and, when required, memory is modified

  • the pc is modified so the next instruction is the instruction following the SWI

  • execution is resumed.


Using Multi-ICE standard semihosting with systems that include time-sensitive interrupt-driven software is not recommended. The processor must be halted while a semihosting operation is performed, and so interrupts will be missed. Use DCC semihosting or ARM RealMonitor to debug these systems

The breakpoint on the SWI vector uses breakpoint resources that might be required for other purposes.

DCC semihosting

DCC semihosting offers two advantages to standard breakpoint-based semihosting:

  • it is in most cases faster

  • it does not cause the target processor to enter debug state and so interrupts continue to be serviced.

Standard semihosting is the initial semihosting mode because DCC semihosting is more intrusive on the target.

Because DCC semihosting does not cause the processor to halt, this method of semihosting is more suitable for real-time systems. It is also more useful for targets that use two or more processors in a JTAG chain, because DCC semihosting does not interfere with automatic starting and stopping of processors.

You cannot use the DCC for other purposes (for example, Channel Viewers) while DCC semihosting is enabled.

The DCC semihosting SWI handler is installed in target memory at the address in the variable semihosting_dcchandler_address. It is vital that:

  • The address is in the range of an ARM branch instruction (approximately ±32MB) from the SWI vector. It must not rely on a negative branch from low memory wrapping around to high memory.

  • The memory that the debugger writes the handler to is unused.

The SWI handler is no more than 0.75KB in size and is written to memory whenever either:

  • DCC semihosting is enabled by setting semihosting_enabled to two

  • semihosting_dcchandler_address is changed and DCC semihosting is already enabled.

The default value for semihosting_dcchandler_address is 0x70000. To change the location of the handler, you must:

  1. Disable semihosting by setting semihosting_enabled to zero.

  2. Change the address of the handler by setting the variable semihosting_dcc-handler_address to a new value.

  3. Enable DCC semihosting by setting semihosting_enabled to two.


With processors that use Rev C or earlier AMBA wrappers you cannot use DCC-hosted semihosting (semihosting_enabled=2). Use semihosting_enabled=1 (stop/start semihosting) instead.

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