4.10.1. Cached data on ARM architecture processors

When debugging a cached processor with an ARM7, ARM9, or ARM10 core, Multi-ICE preserves as much of the cache contents as possible. In the ideal case, it uses the following strategy:

Note

The effectiveness of cache preservation depends on the exact processor and revision being used. In some cases, limitations in the design of the processor prevent Multi-ICE from using this ideal cache preservation strategy. However, it always ensures that no data is lost, and that cache coherency is maintained.

Locked-Down Data

If you invalidate a cache line that is in a lockdown block, any dirty data in the cache line is lost. The lock down remains in effect. Because the cache line has been invalidated, no further cache hits occur for that line, and so that cache line remains unused, even after exiting debug state. Any subsequent accesses to the invalidated addresses instead use the unlocked region of the cache.

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