Adaptive clocking

A technique in which a clock signal is sent out by Multi-ICE and it waits for the returned clock before generating the next clock pulse. The technique allows the Multi-ICE interface unit to adapt to differing signal drive capabilities and differing cable lengths.


See ARM Developer Suite.


See ARM Debugger for UNIX.


See ARM Debugger for Windows.


Angel is a debug monitor that runs on an ARM-based target and enables you to debug applications.

Application Program Interface

A specification for a set of procedures, functions, data structures, and constants that are used to interface two or more software components together. For example, an API between an operating system and the application programs that use it might specify exactly how to read data from a file.

ARM Debugger for UNIX

ARM Debugger for UNIX (ADU) and ARM Debugger for Windows (ADW) are two versions of the same ARM debugger software, running under UNIX or Windows respectively.

ARM Debugger for Windows

ARM Debugger for Windows (ADW) and ARM Debugger for UNIX (ADU) are two versions of the same ARM debugger software, running under Windows or UNIX respectively. This debugger was issued originally as part of the ARM Software Development Toolkit.

ARM Developer Suite

A suite of applications, together with supporting documentation and examples, that enable you to write and debug applications for the ARM family of RISC processors.

ARM eXtended Debugger

The ARM eXtended Debugger (AXD) is the latest debugger software from ARM that enables you to make use of a debug agent in order to examine and control the execution of software running on a debug target. AXD is supplied in both Windows and UNIX versions.


ARMulator is an instruction set simulator. It is a collection of modules that simulate the instruction sets and architecture of various ARM processors.


See ARM eXtended Debugger.


Memory organization where the least significant byte of a word is at a higher address than the most significant byte. See Little-endian.

Cache cleaning

The process of writing dirty data in a cache to main memory.


An additional processor that is used for certain operations, for example, for floating-point math calculations, signal processing, or memory management.

Core Module

See Integrator.


Central Processor Unit.


Current Program Status Register. See Program Status Register.


Data cache.


See Dynamic Linked Library.

Dirty data

When referring to a processor data cache, data that has been written to the cache but has not been written to main memory. Only write-back caches can have dirty data, because a write-through cache writes data to the cache and to main memory simultaneously. The process of writing dirty data to main memory is called cache cleaning.

Double word

A 64-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.

Dynamic Linked Library

A collection of programs, any of which can be called when needed by an executing program. A small program that helps a larger program communicate with a device such as a printer or keyboard is often packaged as a DLL.


See Enhanced Capability Port.


The additional hardware provided by debuggable ARM processors to aid debugging.

Enhanced Capability Port

A standard for parallel ports which enables fast bidirectional data transfers over parallel ports.

See Also EPP and IEEE1284.

Enhanced Parallel Port

A standard for parallel ports which enables fast bidirectional data transfers over parallel ports.

See Also ECP and IEEE1284.


See Enhanced Parallel Port.


The actual hardware and operating system that an application will run on.


Embedded Trace Macrocell.

External Data Representation

A specification defined by Sun Microsystems describing a way of transferring typed data between computer systems in a system independent manner. Used by Sun RPC.

Flash memory

Nonvolatile memory that is often used to hold application code.


A 16-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.


The portion of computer memory that can be used for creating new variables.


A computer which provides data and other services to another computer. Especially, a computer providing debugging services to a target being debugged.


Instruction cache.


See In-Circuit Emulator.

ICE Extension Unit

A hardware extension to the EmbeddedICE logic that provides more breakpoint units.



IEEE 1149.1

The IEEE Standard which defines TAP. Commonly (but incorrectly) referred to as JTAG.

IEEE 1284

A standard for parallel port interfaces which encompasses ECP but extends it to enable semi-autonomous transfers.


See ICE Extension Unit.


An executable file that has been loaded onto a processor for execution.

In-Circuit Emulator

A device enabling access to and modification of the signals of a circuit while that circuit is operating.

Instruction Register

When referring to a TAP controller, a register that controls the operation of the TAP.


An ARM hardware development platform. Core Modules are available that contain the processor and local memory.


See Instruction Register.

Joint Test Action Group

The name of the standards group which created the IEEE 1149.1 specification.


See Joint Test Action Group.


Memory organization where the least significant byte of a word is at a lower address than the most significant byte. See also Big-endian.

Memory management unit

Hardware that controls caches and access permissions to blocks of memory, and translates virtual to physical addresses.


See Memory Management Unit.


Multi-processor EmbeddedICE interface. ARM registered trademark.


Abbreviation of System Reset. The electronic signal which causes the target system other than the TAP controller to be reset. This signal is known as nSYSRST in some other manuals.

See Also nTRST.


Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller to be reset. This signal is known as nICERST in some other manuals.

See Also nSRST.

Open collector

A signal that may be actively driven LOW by one or more drivers, and is otherwise passively pulled HIGH. Also known as a "wired AND" signal.


The ARM Platform-Independent Development card, now known as the ARM Development Board.


A platform-independent evaluator card designed and supplied by ARM Limited.

Port mapper

A process that enables RPC client processes to contact the RPC server process for a particular RPC service.

Processor Core

The part of a microprocessor that reads instructions from memory and executes them, including the instruction fetch unit, arithmetic and logic unit and the register bank. It excludes optional coprocessors, caches, and the memory management unit.

Processor Status Register

See Program Status Register.

Program image

See Image.

Program Status Register

Program Status Register (PSR), containing some information about the current program and some information about the current processor. Often, therefore, also referred to as Processor Status Register.

Is also referred to as Current PSR (CPSR), to emphasize the distinction between it and the Saved PSR (SPSR). The SPSR holds the value the PSR had when the current function was called, and which will be restored when control is returned.


See Remote Debug Interface.


Changing the address of physical memory or devices after the application has started executing. This is typically done to allow RAM to replace ROM once the initialization has been done.


Remote_A is a software protocol converter and configuration interface. It converts between the RDI 1.5 software interface of a debugger and the Angel Debug Protocol used by Angel targets. It can communicate over a serial or Ethernet interface.

Remote Debug Interface

RDI is an open ARM standard procedural interface between a debugger and the debug agent. The widest possible adoption of this standard is encouraged.

Remote Procedure Call

A call to a procedure in a different process. The calling procedure invokes a procedure in a different process that is usually running on a different processor.




See Remote Procedure Call.


Returned TCK. The signal which enables Adaptive Clocking.


Real Time Operating System.

Scan Chain

A group of one or more registers from one or more TAP controllers connected between TDI and TDO, through which test data is shifted.


A mechanism whereby the target communicates I/O requests made in the application code to the host system, rather than attempting to support the I/O itself.


Saved Program Status Register. See Program Status Register.


Software Interrupt. An instruction that causes the processor to call a programer-specified subroutine. Used by ARM to handle semihosting.

Synchronous starting

Setting several processors to a particular program location and state, and starting them together.

Synchronous stopping

Stopping several processors in such a way that they stop executing at the same instant.


A specific form of RPC defined as a standard by Sun Microsystems that uses the XDR standard and TCP/IP datagrams to communicate between networked computers.


See Test Access Port.

TAP Controller

Logic on a device which allows access to some or all of that device for test purposes. The circuit functionality is defined in IEEE1149.1.

See Also TAP, IEEE1149.1.


The name of the interface API between the Multi-ICE Server and its clients.


The actual processor (real silicon or simulated) on which the application program is running.


The electronic clock signal which times data on the TAP data lines TMS, TDI, and TDO.


The electronic signal input to a TAP controller from the data source (upstream). Usually this is seen connecting the Multi-ICE Interface Unit to the first TAP controller.


The electronic signal output from a TAP controller to the data sink (downstream). Usually this is seen connecting the last TAP controller to the Multi-ICE Interface Unit.

Test Access Port

The port used to access a device's TAP Controller. Comprises TCK, TMS, TDI, TDO and nTRST (optional).


Transistor-transistor logic. A type of logic design in which two bipolar transistors drive the logic output to one or zero. LSI and VLSI logic often used TTL with HIGH logic level approaching +5V and LOW approaching 0V.


A location within the image that will be monitored and that will cause execution to stop when it changes.


A 32-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.


See External Data Representation.

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