E.6. ARM925T processor registers

Table E.7 describes the ARM925T processor registers.

Table E.7. ARM925T processor registers

Register

Description

Access

Data

c0

ID register

Read-only

Read-only

ID information

Cache configuration[1]

c1

Control register

Read/write

Configuration flags

c2

Translation Table Base

Read/write

Translation table base

c3

Domain Access Control

Read/write

Access flags

c5

Fault Status register

Read/write

Status info

c6

Fault Address register

Read/write

Fault address

c7

Cache operations:

  • Invalidate ICache and DCache

  • Invalidate ICache

  • Invalidate I single entry (VA)

  • Prefetch ICache Line

  • Invalidate DCache

  • Invalidate D single entry (VA)

  • Invalidate D single entry (index)

  • Clean entire DCache

  • Clean D single entry (VA)

  • Clean and Invalidate D single entry

  • Clean D single entry (index)

  • Clean and Invalidate D single entry (index)

  • Drain Write Buffer

Write-only

SBZ

SBZ

VA

VA

SBZ

VA

Index and segment

SBZ

VA

VA

Index and segment

Index and segment

SBZ

c8

TLB operations:

  • Invalidate ITLB and DTLB

  • Invalidate ITLB

  • Invalidate ITLB single entry (VA)

  • Invalidate DTLB

  • Invalidate DTLB single entry (VA)

Read/write

SBZ

SBZ

VA

SBZ

VA

c10

TLB lockdown control:

  • Data Lockdown Base

  • Instruction Lockdown Base

Read/write

Base and victim

Base and victim

c13

Process ID

Read/write

Process ID

c15

TI specific registers:

  • I-max

  • I-min

  • Thread ID

  • ARM925T status register

Read/write

Configuration bits

I-max

I-min

Thread ID

Status bits

[1] Revision 1 onwards.

The encodings to read or write the registers are as follows:

c0

A data read with cp15_cache_selected = 0 accesses the ID register.

A data read with cp15_cache_selected = 1 accesses the Cache Configuration register.

c1, c2, c3

All data reads and writes occur as expected.

c5

All data reads and writes access the FSR, which only records Data Aborts. Prefetch Aborts (caused by faulting an instruction access) are not recorded.

c6

All data reads and writes access the FAR, which only records Data Aborts. Prefetch Aborts (caused by faulting an instruction access) are not recorded.

c7

The function performed is determined by the value of the cp15_cache_selected variable, and by bits [2:0] of the data that is written, as shown in Table E.8.

Table E.8. ARM925T cp15 register 7 accesses

cp15_cache_selected

Bit 2

Bit 1

Bit 0

Purpose

1

0

0

0

Invalidate ICache and DCache

1

0

0

1

Invalidate ICache

1

0

1

0

Invalidate I single entry (VA)

1

0

1

1

Prefetch ICache Line (VA)

110

0

Drain Write Buffer

0

0

0

0

Invalidate DCache

0

0

0

1

Invalidate D single entry

0

0

10

Invalidate D single entry (index)

0011Clean entire DCache

0

100

Clean D single entry (VA)

0

101

Clean and Invalidate D single entry (VA)

0

1

1

0

Clean D single entry (index)

0

1

1

1

Clean and Invalidate D single entry (index)

The encoded function uses bits [31:3] of the data that is written, with bits [2:0] cleared.

c8

The function performed is determined by the value of the cp15_cache_selected variable, and by bits [1:0] of the data that is written, as shown in Table E.9.

Table E.9. ARM925T cp15 register 8 accesses

cp15_cache_selected

Bit 1

Bit 0

Purpose

100Invalidate ITLB and DTLB
101Invalidate ITLB
110Invalidate ITLB single entry (VA)
000Invalidate DTLB
001Invalidate DTLB single entry (VA)

The encoded function uses bits [31:2] of the data that is written, with bits [1:0] cleared.

c10

A data read or write with cp15_cache_selected = 0 accesses the Data TLB Lockdown register.

A data read with cp15_cache_selected = 1 accesses the Instruction TLB Lockdown register.

c13

All data reads and writes occur as expected.

c15

The function performed is determined by the value of the cp15_current_memory_area variable (although the functions are not related to memory areas), as shown in Table E.10.

Table E.10. ARM925T cp15 register 7 accesses

cp15_current_memory_area

Access

Purpose

0

Read/write

ARM925T configuration register

1

Read/write

I-max

2

Read/write

I-min

3

Read/write

Thread ID

4

Read only

ARM925T status register

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