6.5. JTAG signal integrity and maximum cable lengths

For JTAG-based debugging, you must have a very reliable connection between Multi-ICE and the target board because there is no way to detect or correct errors. For this reason it is important to guarantee good signal integrity.

One factor that can limit the maximum cable length is propagation delays. Normally the Multi-ICE interface unit samples data returning from the target using the same clock as for sending data, TCK. If the propagation delay gets too long then the Multi-ICE interface unit samples the signal at the wrong time. This can be resolved by using adaptive clocking. In this mode the target returns a clock, RTCK, and Multi-ICE does not sample data on TDO, or send further data on TDI, until clocked by this signal.

In an ASIC or ASSP (for example, in ARM processor based microcontrollers) the TDO and RTCK signals are not typically implemented with a stronger driver than other signals on the device. The strength of these drivers varies from device to device. An example specification is to sink or source 4mA. Many designs connect these pins on the device directly to the corresponding pins on the Multi-ICE connector.

Over very short lengths of cable, such as the one supplied with Multi-ICE, this type of weak driver is adequate. However, if longer cables are used then the cable becomes harder to drive as the capacitive load increases. When using longer cables it becomes essential to consider the cable as a transmission line and to provide appropriate impedance matching, otherwise reflections occur.

Multi-ICE has much stronger drivers and they are connected through 100O series resistors to impedance match with the JTAG cable. The output circuitry of Multi-ICE can easily sink or source over 40mA of current. This is very much better than the typical circuit used at the target end.

With the typical situation at the target end (weak drivers, no impedance matching resistors) you can only expect reliable operation over short cables (approximately 20cm). If operation over longer cables is required you must improve the circuitry used at the target end.

The recommended solution is to add an external buffer with good current drive and a 100O series resistor for the TDO (and RTCK if used) signals on your target board. Using this technique you can debug over a significantly longer cable, up to several metres. Depending on cable length and propagation delays through your buffers and cables it might still be necessary to use adaptive clocking.

If you are not already using adaptive clocking in your design, you can generate RTCK at the target end by using the TCK signal fed through the same buffer and impedance matching circuit as used for TDO. If even longer cables are required, another solution is to buffer the JTAG signals through differential drivers, for example, RS422 and connect to differential receivers at the remote end using twisted pair cable. You must use adaptive clocking to allow for propagation delays in the cable and drivers. Reliable operation is possible over tens of metres using this technique.

Reducing the JTAG clock speed in the Multi-ICE server avoids some, but not all, of the problems associated with long cables. If reducing the speed of downloading code and reading memory in the debugger is not a significant problem, try experimenting with lowering this clock speed.

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