4.5.2. Internal variable support by processor

The set of variables that is available depends partly on the processor that is selected. For example, variables relating to the system coprocessor are not available on processors that do not have a system coprocessor.

Table 4.1, Table 4.2, and Table 4.3 describe the variables available for each processor group. For a description of the function and allowed values of the variables see Internal variable descriptions.

Variables marked with a delta ? are not used by the AXD debugger in ADS v1.1 (or a later version). AXD and Multi-ICE Version 2.1 (or later) both support a mechanism that describes the target to the debugger, making these variables unnecessary.

Variables marked with a sigma S are incorporated into the AXD properties interface and do not appear in the debugger internals variable list.

Table 4.1. ARM7 family debugger variable support

Variable nameARM7[1]ARM7T[2]Samsung[3]ARM7xxT[4]ARM7EJ-S
cp_access_code_address

Yes

YesYesYesNo
cp15_current_memory_area ?

No

NoNoYes[5]No
icebreaker_lockedpointsYesYesYesYesYes
internal_cache_enabled

Yes

YesYesYesYes
internal_cache_flush

Yes

YesYesYesYes
ks32c_special_base_address

No

NoYesNoNo
safe_non_vector_address

Yes

YesYesYesYes
semihosting_dcchandler_address S[6]

No

YesYesYesYes
semihosting_enabled =0 or =1 S

Yes

YesYesYesYes
semihosting_enabled =2 S

No

YesYesYesYes
sw_breakpoints_preferred

Yes

YesYesYesYes
system_reset

Yes

YesYesYesYes
top_of_memory

Yes

YesYesYesYes
user_input_bit [1,2]

Yes

YesYesYesYes
user_output_bit [1,2]

Yes

YesYesYesYes
vector_address

No

NoNoYes[7]Yes[8]

[1] ARM7 includes ARM7DI, ARM7DMI, and devices using these cores.

[2] ARM7T includes ARM7TDI, ARM7TDMI, ARM7TDI-S, ARM7TDMI-S, and devices using these cores.

[3] Samsung includes the KS32C50100 and the S3C4510B.

[4] ARM7xxT includes ARM710T™, ARM720T™, and ARM740T™.

[5] Only ARM740T.

[6] This must be in the range of an ARM branch instruction (approximately ±32MB) from the SWI vector. It must not rely on a negative branch from low memory wrapping around to high memory.

[7] Only ARM720T.

[8] There is no system coprocessor.

Table 4.2. ARM9 family debugger variable support

Variable nameARM9T[1]ARM9xxT[2]ARM9E-SARM9xxE-S[3]
cp_access_code_addressNoYesNoYes
cp15_cache_selected ?NoYesNoYes
cp15_current_memory_area ?NoYes[4]NoYes[5]
icebreaker_lockedpointsYesYesYesYes
internal_cache_enabledYesYesYesYes
internal_cache_flushYesYesYesYes
safe_non_vector_addressYesYesYesYes
semihosting_dcchandler_address S[6]YesYesYesYes
semihosting_enabled SYesYesYesYes
sw_breakpoints_preferredYesYesYesYes
system_resetYesYesYesYes
top_of_memoryYesYesYesYes
user_input_bit [1,2]YesYesYesYes
user_output_bit [1,2]YesYesYesYes
vector_addressNoYes[7]Yes[8]Yes

[1] ARM9T includes ARM9TDMI™ and devices using the cores.

[2] ARM9xxT includes ARM920T, ARM922T™, ARM925T™, and ARM940T.

[3] Includes ARM926EJ-S, ARM946E-S, and ARM966E-S.

[4] Only ARM940T.

[5] Only ARM946E-S.

[6] This must be in the range of an ARM branch instruction (approximately ±32MB) from the SWI vector. It must not rely on a negative branch from low memory wrapping around to high memory.

[7] Excludes ARM940T (Rev 0).

[8] There is no system coprocessor.

Table 4.3. ARM10 family and XScale microarchitecture debugger variable support

Variable nameARM10[1]

XScale

cp15_cache_selected ?Yes

No

icebreaker_lockedpointsNoNo
internal_cache_enabledYes

Yes

internal_cache_flushYes

Yes

safe_non_vector_addressNo

No

semihosting_dcchandler_address S[2]Yes

No

semihosting_enabled SYes

Yes

sw_breakpoints_preferredYes

Yes

system_resetYes

Yes

top_of_memoryYes

Yes

user_input_bit [1,2]

Yes

Yes

user_output_bit [1,2]Yes

Yes

vector_addressYes

Yes

[1] Includes ARM1020T, and ARM10200T.

[2] This must be in the range of an ARM branch instruction (approximately ±32MB) from the SWI vector. It must not rely on a negative branch from low memory wrapping around to high memory.

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