4.5.3. Internal variable descriptions

This is a list of the debugger internal variables that Multi-ICE makes available to you through the debugger. Refer to the manual for your debugger for information on reading and writing them:

cp_access_code_address

This specifies an area of memory, of at least 40 bytes, that can be used by Multi-ICE during read or write coprocessor operations. Multi-ICE ensures that this memory is reloaded with its original values after use. This area of memory must be readable, writable, and executable.

cp15_cache_selected

This is only valid on Harvard Architecture processors. This includes the ARM9 and ARM10 families, but excludes the ARM7 family. It is not valid with XScale processors.

Note

If you are using AXD, this variable is not available. Instead, Multi-ICE describes the target coprocessor register names and access information to AXD. AXD includes the described registers in the processor register view, enabling you to read and modify the values as required.

It indicates the alias of the CP15 register that is read/written. Use one of the values from Table 4.4.

Table 4.4. Cache selection type values

Value CPU typeDescription
0ARM9 or ARM10 (Harvard) coresSelect the Data Cache (DCache)
1ARM9 or ARM10 (Harvard) coresSelect the Instruction Cache (ICache)
2ARM946E-S, ARM966E-SSelect tightly-coupled instruction memory
3ARM946E-S, ARM966E-SSelect tightly-coupled data memory

For further information on the CP15 registers, refer to Appendix E CP15 Register Mapping, and to the ARM technical reference manual for the processor being used.

cp15_current_memory_area (0-7=Memory areas 0-7)

This selects the memory area to be accessed in register 6 on processors that support multiple protection regions. If necessary, the cp15_cache_selected variable selects between a data or instruction memory area.

For further information on the CP15 registers, refer to Appendix E CP15 Register Mapping, and to the ARM technical reference manual for the processor being used.

Note

If you are using AXD, this variable is not available. Instead, Multi-ICE describes the target coprocessor register names and access information to AXD. AXD includes the described registers in the processor register view, enabling you to read and modify the values as required.

icebreaker_lockedpoints

This variable controls user access to the EmbeddedICE logic watchpoint registers. It is a bitmask, with bit 0 relating to watchpoint unit 0 and bit 1 relating to watchpoint unit 1. If an IEU is built into the processor, then bit 2 relates to IEU unit 0, bit 3 to IEU unit 1, up to bit 31 relating to IEU unit 29.

If a bit in the bitmask is set (1) then Multi-ICE does not use the related watchpoint unit. If it is unset (0), then Multi-ICE can use the unit. Refer to Using the EmbeddedICE logic values for more information.

internal_cache_enabled (0=disabled, 1=enabled)

This variable controls the behavior of the memory cache within the Multi-ICE DLL. On AXD startup, it has the same value as the Cache Enabled flag in the Multi-ICE Advanced Settings window. The user can then change this value to override the initial value, and so enable or disable the cache.

internal_cache_flush

This variable always reads as 0. Writing a nonzero value to it causes the Multi-ICE internal memory cache to be flushed.

ks32c_special_base_address

This variable contains the address of the special system registers in the Samsung KS32C50100 or Samsung S3C4510B processor. These registers can be mapped to one of many pages of memory, and it is not possible to ask the device where they are. One register from this bank is required by the Multi-ICE cache manipulation code.

safe_non_vector_address

This variable defaults to 0x10000. This variable must be set to the base address of a 64KB area of memory that does not overlap the 64KB block of memory starting at vector_address. The block of memory that is referenced must be safe, in that the Multi-ICE DLL might cause some reads from this area to occur, and these reads must be harmless. Memory reads must not cause Data Aborts and must not affect I/O devices. Multi-ICE does not write to this memory area.

semihosting_dcchandler_address

When the value of semihosting_enabled is 2, the value of semihosting_dcchandler_address is the address of the SWI handler. See Semihosting.

semihosting_enabled

This variable controls the semihosting facility in the Multi-ICE DLL. See Semihosting.

sw_breakpoints_preferred

This variable controls the breakpoint selection algorithm. If it is nonzero, the breakpoint selection algorithm chooses to use software breakpoints wherever possible (for example, it does not set software breakpoints in ROM).

If it is zero, it chooses to use hardware breakpoints unless the number of breakpoints required exceeds the number of hardware breakpoint units available. See Appendix B Breakpoint Selection Algorithm for more information.

system_reset

When read, this is always zero. If written with a nonzero value the target board is immediately reset using system reset pulse of approximately 250ms.

top_of_memory

This variable defines the highest address in memory that the C-library uses for stack space. The value is transferred to the target in the result of the SYS_HEAPINFO semihosting SWI call. The default value is 0x80000, meaning that the first word pushed to the stack is written to 0x7FFFC.

For the purposes of SYS_HEAPINFO, Multi-ICE assumes the memory map shown in Figure 4.21.

Figure 4.21. Relating top_of_memory to single section program layout

Note

  • If the application is scatterloaded the application must include a user-defined function (__user_initial_stackheap) that defines the stack and heap limits. Therefore, if the application does not call SYS_HEAPINFO explicitly, the target ignores the value of top_of_memory.

  • The value of top_of_memory must be higher than the sum of the program base address and program size. If set incorrectly, the program might crash because of stack corruption or because the program overwrites its own code.

  • There is no requirement that top_of_memory is at the true top of memory. A C or assembler program can use memory at higher addresses.

user_input_bit1, user_input_bit2

These variables show the state of the two user input bits. These are not polled, so they show the state at the time the Debugger Internals window was displayed, the core was last stopped, or the command-line command was executed.

user_output_bit1, user_output_bit2

These variables allow you to alter the state of the user output bits. You can only change the output bits if they are assigned to this connection, and if the Set by Driver option is enabled. These are set on the server using User Output Bits, found under the Settings menu (see User output bits dialog). These are not polled, so they show the state at the time the Debugger Internals window was displayed or the command-line command was executed.

vector_address

This variable applies only to processors that support movable vector tables, such as ARM720T™ and ARM920T. It tells Multi-ICE where the exception vector table is. The default value is the vector address that was current the last time the processor stopped. The address is determined by reading the V bit from CP15 Register 1. You can set it to either 0 or 0xFFFF0000. There must be readable memory at this address.

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