1.3.1. Debug extensions to the ARM core

The extensions consist of a number of scan chains around the processor core and some additional signals that are used to control the behavior of the core for debug purposes. The most significant of these additional signals are:


This core signal enables external hardware to halt processor execution for debug purposes. When HIGH, the current memory access is tagged as breakpointed and the core stops when this instruction is executed.


This core signal is a level-sensitive input that causes the CPU core to enter debug state when the current instruction has completed.


This core signal is an output from the CPU core that goes HIGH when the core is in debug state allowing external devices to determine the current state of the core.

Multi-ICE uses these, and other signals, by using the debug interface of the processor core, for example by writing to the control register of the EmbeddedICE logic. For more details, refer to the debug interface section of the ARM datasheet or technical reference manual for your core.

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