6.2.2. Using adaptive clocking to synchronize the JTAG port

ARM-based devices using only hard macrocells, for example ARM7TDMI and ARM920T, use the standard five-wire JTAG interface (TCK, TMS, TDI, TDO, and nTRST). Some target systems, however, require that JTAG events are synchronized to a clock in the system. To handle this case an extra signal is included on the JTAG port. For example, this synchronization is required in:

The adaptive clocking feature of Multi-ICE addresses this requirement. When adaptive clocking is enabled, Multi-ICE issues a TCK signal and waits for the RTCK (Returned TCK) signal to come back. Multi-ICE does not progress to the next TCK until RTCK is received.


  • If you use the adaptive clocking feature, transmission delays, gate delays, and synchronization requirements result in a lower maximum clock frequency than with non-adaptive clocking. Do not use adaptive clocking unless it is required by the hardware design.

  • If, when autoconfiguring a target, the Multi-ICE interface unit receives pulses on RTCK in response to TCK it assumes that adaptive clocking is required, and enables adaptive clocking in the target configuration. If the hardware does not require adaptive clocking, the target is driven slower than it could be. You can disable adaptive clocking using controls on the JTAG settings dialog.

You can use adaptive clocking as an interface to targets with slow or widely varying clock frequency, such as battery-powered equipment that varies its clock speed according to processing demand. In this system, TCK might be hundreds of times faster than the system clock, and the debugger loses synchronization with the target system. Adaptive clocking ensures that the JTAG port speed automatically adapts to slow system speed.

Figure 6.1 illustrates a circuit for basic applications, with a partial timing diagram shown in Figure 6.2. The delay can be reduced by clocking the flip-flops from opposite edges of the system clock, because the second flip-flop only provides better immunity to metastability problems. Even a single flip-flop synchronizer never completely misses TCK events, because RTCK is part of a feedback loop controlling TCK.

Figure 6.1. Basic JTAG port synchronizer

Figure 6.2. Timing diagram for the Basic JTAG synchronizer in Figure 6.1

It is common for an ASIC design flow and its design rules to impose a restriction that all flip-flops in a design are clocked by one edge of a single clock. To interface this to a JTAG port that is completely asynchronous to the system, it is necessary to convert the JTAG TCK events into clock enables for this single clock, and to ensure that the JTAG port cannot overrun this synchronization delay. Figure 6.3 shows one possible implementation of this circuit, and Figure 6.4 shows a partial timing diagram, showing how TCKFallingEn and TCKRisingEn are each active for exactly one period of CLK. It also shows how these enable signals gate the RTCK and TDO signals so that they only change state at the edges of TCK.

Figure 6.3. JTAG port synchronizer for single rising-edge D-type ASIC design rules

Figure 6.4. Timing diagram for the D-type JTAG synchronizer in Figure 6.3

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