6.2.3. Reset signals

This section describes the reset signals that are available on ARM devices and how Multi-ICE expects them to be wired. It is presented in the following sections:

ARM reset signals

All ARM cores have a main processor reset that might be called nRESET, BnRES, or HRESET. This is asserted by one or more of these conditions:

  • power on

  • manual push button

  • remote reset from the debugger (using Multi-ICE)

  • watchdog circuit (if appropriate to the application).

Any ARM processor core including the JTAG interface has a second reset input called nTRST (TAP Reset). This resets the EmbeddedICE logic, the TAP controller, and the boundary scan cells. This is activated by one or more of these conditions:

  • power on

  • remote JTAG reset (from Multi-ICE).

It is strongly recommended that both signals are separately available on the JTAG connector. If the nRESET and nTRST signals are linked together, resetting the system also resets the TAP controller. This means that:

  • it is not possible to debug a system from reset, because any breakpoints previously set are lost

  • you might have to start the debug session from the beginning, because Multi-ICE does not recover when the TAP controller state is changed.

Multi-ICE reset signals

The Multi-ICE interface unit has two reset signals connected to the debug target board:

  • nTRST drives the JTAG nTRST signal on the ARM processor core. It is an open collector output that is activated whenever the Multi-ICE software has to re-initialize the debug interface in the target system.

  • nSRST is a bidirectional signal that both drives and senses the system reset signal on the target board. The open collector output is driven LOW by the debugger to re-initialize the target system.

The target board must include a pull-up resistor on both reset signals.

Example reset circuits

The circuits shown in Figure 6.5 and Figure 6.6 illustrate how the behavior described in Reset signals can be achieved. The MAX823 used in Figure 6.6 is a typical power supply supervisor. It has a current limited nRESET output that can be overdriven by the Multi-ICE interface unit.

When the Multi-ICE server detects a reset, it records this event so that clients can find out about it when they next ask for the target status. The record is kept for each active connection, so that one client cannot prevent another client from finding out about the reset. This is particularly useful if the target system is using a watchdog reset circuit because there might be no other evidence that the system has reset.

Figure 6.5. Example reset circuit logic

Figure 6.6. Example reset circuit using power supply monitor ICs

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