6.3.1. ICs containing multiple devices

The JTAG standard originally described daisy-chaining multiple devices on a PCB. This concept is now extended to multiple cores within a single package. If more than one JTAG TAP controller is present within your ASIC, they must all be serially chained so that Multi-ICE can communicate with all of them simultaneously. The chaining can either be within the ASIC or external to it.

There are a few possible configurations of multiple TAP controllers:

TAP controllers serially chained within the ASIC

This is the natural extension of the JTAG board-level interconnection, and is the one recommended for use with Multi-ICE. There is no increase in package pin count, and only a very small impact on speed because unaddressed TAP controllers can be put into bypass mode, as shown in Figure 6.7.

Figure 6.7. TAP Controllers serially chained in an ASIC

Each set of JTAG connections is pinned out separately

This gives the greatest flexibility on the PCB, but at the cost of many pins on the device package. If this method is chosen to simplify device testing, the JTAG ports must be serially chained on the PCB when Multi-ICE is to be used. The separate JTAG ports can be tracked to separate headers on the PCB, but this then requires one Multi-ICE interface unit per header, and is unnecessary.

Multiplexing of data signals

There is no support in Multi-ICE for multiplexing TCK, TMS, TDI, TDO, and RTCK, between a number of different processors.

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