Multi-ICE® User Guide 5.1.3. The debugger reports “Target processor would not enter debug state when requested. Do you want to try asserting System Reset with a breakpoint on address 0?”

5.1.3. The debugger reports “Target processor would not enter debug state when requested. Do you want to try asserting System Reset with a breakpoint on address 0?”

The debugger has tried to use Multi-ICE to access the processor, for example, to stop it, but when the Multi-ICE DLL tried to do this the processor did not respond as expected. This could be because:

The JTAG clock frequency is too high for this device or this cable length. Try a lower clock frequency.
The server has been incorrectly configured manually (incorrect number, type, or order of devices, or incorrect IR length given in IRlength.arm file).
The processor is being held in reset state.
The processor signal DBGEN is held LOW (deasserted), preventing the DBGRQ being recognized.
The processor memory interface signal nWAIT (or the equivalent bus signals BWAIT and HWAIT) are permanently asserted, or there is no processor core clock. The processor only acknowledges DBGRQ at the end of an instruction, and so anything that prevents the current instruction terminating also prevents the processor entering debug state.
One or more of the JTAG signals, most often TCK, are not of sufficient quality. This can result from a variety of problems in the design of the PCB or the length and type of wiring.
If the device can be autoconfigured (see The Multi-ICE server fails to autoconfigure the chip) but does not work reliably, there is a problem with JTAG signal quality. If you manually configure the server, you get the error message Can't stop processor.

You can often regain control of the processor by placing a breakpoint on location zero and then resetting the processor, but this cannot be done without resetting the whole of the target, including any other processors connected to the JTAG chain. Therefore, Multi-ICE asks if it is acceptable to do this.

Note

This method of gaining access to the processor does not work properly unless the system reset nSRST and TAP reset line nTRST are connected independently, as described in Chapter 6 System Design Guidelines, because Multi-ICE must be able to program the TAP controller while the processor is in reset.

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