F.1.1. JTAG pinouts

Table F.1 shows the JTAG pinouts.

Table F.1. JTAG pinouts

Pin

Signal

I/O

Description

Pin 1

VTref

Input

This is the target reference voltage. It indicates that the target has power and it is also used to create the logic-level reference for the input comparators on TDO and RTCK. It also controls the output logic levels to the target. It is normally fed from Vdd on the target board and might have a series resistor (though this is not recommended).

Pin 2

Vsupply

Input

This is the supply voltage to Multi-ICE. It draws its supply current from this pin through a step-up voltage convertor. This is normally fed by the target Vdd which must not have a series resistor in the feed to this pin. If the target supply voltage or its current capability is too LOW, this path is broken by an external power jack on the EmbeddedICE adaptor.

Pin 3

nTRST

Output

Open collector output from Multi-ICE to the Reset signal on the target JTAG port. This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.

Pin 4

GND

-

Ground.

Pin 5

TDI

Output

Test Data In signal from Multi-ICE to the target JTAG port. It is recommended that this pin is pulled to a defined state.

Pin 6

GND

-

Ground.

Pin 7

TMS

Output

Test Mode signal from Multi-ICE to the target JTAG port. This pin must be pulled up on the target so that the effect of any spurious TCKs when there is no connection is benign.

Pin 8

GND

-

Ground.

Pin 9

TCK

Output

Test Clock signal from Multi-ICE to the target JTAG port. It is recommended that this pin is pulled to a defined state.

Pin 10

GND

-

Ground.

Pin 11

RTCK

Input

Return Test Clock signal from the target JTAG port to Multi-ICE. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. Multi-ICE provides Adaptive Clock Timing, which waits for TCK changes to be echoed correctly before making further changes. Targets that do not have to process TCK can simply ground this pin.

Pin 12

GND

-

Ground.

Pin 13

TDO

Input

Test Data Out from the target JTAG port to Multi-ICE.

Pin 14

GND

-

Ground.

Pin 15

nSRST

Input/output

Open collector output from Multi-ICE to the target system reset. This is also an input to Multi-ICE so that a reset initiated on the target can be reported to the debugger.

This pin must be pulled up on the target to avoid unintentional resets when there is no connection.

Pin 16

GND

-

Ground.

Pin 17

DBGRQ

-

This pin is not connected in the Multi-ICE interface unit. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system.

Pin 18

GND

-

Ground.

Pin 19

DBGACK

-

This pin is not connected in the Multi-ICE interface unit. It is reserved for compatibility with other equipment to be used as a debug acknowledge signal from the target system.

Pin 20

GND

-

Ground.

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