Multi-ICE ® UserGuide

Version 2.2

Table of Contents

About this document
Intended audience
Typographical conventions
Timing diagram conventions
Further reading
Feedback on Multi-ICE
Feedback on this document
1. Introduction
1.1. About Multi-ICE
1.2. Availability and compatibility
1.3. Basic principles
1.3.1. Debug extensions to the ARM core
1.3.2. The EmbeddedICE logic
1.3.3. The ICE extension unit
1.3.4. How Multi-ICE differs from a debugmonitor
1.4. Introduction to the Multi-ICE components
1.4.1. The Multi-ICE interface unit
1.4.2. The Multi-ICE parallel port driver
1.4.3. The Multi-ICE server
1.4.4. The portmap application
1.4.5. The Multi-ICE DLL
1.5. New features and changes from previousversions
1.5.1. New features in Multi-ICE Version 2.2
1.5.2. Changes in Multi-ICE Version 2.2
1.5.3. New features in Multi-ICE Version 2.1
1.5.4. Changes in Multi-ICE Version 2.1
1.5.5. New features in Multi-ICE Version 2.0
1.5.6. Changes in Multi-ICE Version 2.0
1.5.7. New features in Release 1.4
2. Getting Started
2.1. System requirements
2.1.1. Host software requirements
2.1.2. Host hardware requirements
2.1.3. Target hardware requirements
2.2. Connecting the Multi-ICE hardware
2.2.1. What you require
2.2.2. Connection instructions
2.3. Connecting to nonstandard hardware
2.3.1. Compatibility with PID, PIE, and PIVARM development boards
2.3.2. Nonstandard connectors
2.3.3. Power supply
2.4. Starting the software
2.4.1. Microsoft Windows start program menufor Multi-ICE
2.4.2. Starting the Multi-ICE server
2.4.3. Other Multi-ICE server startup features
3. Using the Multi-ICE Server
3.1. About the Multi-ICE server menus
3.1.1. Menu structure
3.1.2. File menu
3.1.3. View menu
3.1.4. Run control menu
3.1.5. Connection menu
3.1.6. Settings menu
3.1.7. Help menu
3.2. Multi-ICE server device configurationfiles
3.2.1. Automatic device configuration
3.2.2. Manual device configuration
3.3. Server configuration
3.3.1. Chip driver settings dialog
3.3.2. Start-up Options dialog
3.3.3. Parallel port settings dialog
3.3.4. User output bits dialog
3.3.5. User input bits
3.3.6. JTAG settings dialog
3.4. Using the Multi-ICE server with multipleprocessors
3.4.1. Controlling device execution
3.4.2. Run control and the debugger
3.4.3. About run control
3.4.4. Setting up interaction between devices
3.4.5. Setting up the poll frequency
4. Debugging with Multi-ICE
4.1. Compatibility with ARM debuggers
4.2. Connecting Multi-ICE to ADW, ADU,or AXD
4.2.1. Connecting AXD
4.2.2. Connecting ADW and ADU
4.3. Configuring the Multi-ICE DLL
4.3.1. Connect configuration tab
4.3.2. Processor SettingsTab
4.3.3. Advanced configurationtab
4.3.4. Board configurationtab
4.3.5. Trace configurationtab
4.3.6. About Multi-ICE tab
4.3.7. Channel viewer configurationtab
4.3.8. Persistence of DLLsettings
4.4. Configuring and debugging multipleprocessors
4.4.1. Configuration using named AXD targetconfigurations
4.4.2. Configuration using session files
4.5. Debugger internal variables
4.5.1. Accessing debugger internal variables
4.5.2. Internal variable support by processor
4.5.3. Internal variable descriptions
4.6. Post-mortem debugging
4.6.1. Powering the interface unit usingthe power jack (Multi-ICE Version 2.1 or later)
4.6.2. Powering the interface unit usinga modified cable
4.6.3. Powering the interface unit usingthe 14-way JTAG adaptor, HPI-0027
4.7. Access to CP15
4.8. Semihosting
4.8.1. Enabling semihosting
4.8.2. Adding an application SWI handlerwhen using Multi-ICE
4.9. Watchpoints and breakpoints
4.9.1. Watchpoints
4.9.2. Breakpoints
4.9.3. Watchpoints, breakpoints, and theprogram counter
4.9.4. EmbeddedICE/RT breakpoints
4.9.5. Vector breakpoints and exceptions
4.9.6. Vector catch with ROM at 0x0
4.9.7. Stopping the processor
4.10. Cached data
4.10.1. Cached data on ARM architecture processors
4.10.2. Cached data on XScale microarchitectureprocessors
4.11. Debugging applications in ROM
4.11.1. Debugging from reset
4.11.2. Debugging systems with ROM at zero
4.12. Accessing the EmbeddedICE logic directly
4.12.1. Reading EmbeddedICE logic registersfrom AXD
4.12.2. Reading EmbeddedICE logic registersfrom ADW
4.12.3. Using the EmbeddedICE logic values
4.12.4. Support for the ICE Extension Unit
5. Troubleshooting
5.1. Troubleshooting
5.1.1. The Multi-ICE serverfails to autoconfigure the chip
5.1.2. The debugger reports “Attempt to forcethe processor to enter debug state failed - execution continues”
5.1.3. The debugger reports “Target processorwould not enter debug state when requested. Do you want to try assertingSystem Reset with a breakpoint on address 0?”
5.1.4. The debugger reports “*** Data abort***” in the execution window
5.1.5. Random stopping or failure to startthe debugger
5.1.6. The debugger reports “Hardware interfacetimeout”
5.1.7. The debugger reports “Unable to setvector catch breakpoints on exception vectors”
5.1.8. Data aborts or crashes when loadingor running applications
5.1.9. DCC semihosting, the channel viewer,or the DCC fails
5.1.10. A program that prints strings seemsto load and run, but displays garbled text
5.1.11. A 'C' program including string handlingor uses char arrays works on some ARM processors but not on others
5.1.12. When trying to connect Multi-ICE anda logic analyzer to an ARM Integrator board to trace a program,Multi-ICE continually reports "The target is being reset, unableto connect"
5.1.13. My application works using ARMulatorbut quickly crashes when I use Multi-ICE
5.1.14. Running the Multi-ICE server makesmy computer run very slowly
5.1.15. I cannot connect to a Multi-ICE serverfrom the computer that is running it
5.2. Error messages
5.2.1. Multi-ICE server messages
5.2.2. Multi-ICE DLL messages
6. System Design Guidelines
6.1. About the system design guidelines
6.2. System design
6.2.1. Mixing ARM cores with other devices
6.2.2. Using adaptive clocking to synchronizethe JTAG port
6.2.3. Reset signals
6.3. ASIC guidelines
6.3.1. ICs containing multiple devices
6.3.2. Constraints imposed by the Multi-ICEserver
6.3.3. Boundary scan test vectors
6.4. PCB guidelines
6.4.1. PCB connections
6.4.2. Target interface logic levels
6.5. JTAG signal integrity and maximumcable lengths
6.6. Compatibility with EmbeddedICE interfacetarget connectors
6.6.1. Adaptor to connect a Multi-ICE interfaceunit to 14-way connectors
A. Server Configuration File Syntax
A.1. IR length configuration file
A.1.1. File syntax
A.1.2. Device aliases
A.2. Device configuration file
A.2.1. Syntax
A.2.2. Example configuration file
B. Breakpoint Selection Algorithm
B.1. Multi-ICE internal breakpoints
B.2. How the debugger steps and runs code
B.3. Breakpoint and watchpoint allocation algorithm
C. Command-line Syntax
C.1. Multi-ICE server
D. Processor-specific Information
D.1. The ARM1020T (Rev 0) processor
D.1.1. Limitations of the ARM1020T (Rev 0)processor
D.2. Intel XScale microarchitecture processors
D.2.1. Behavior on system reset
D.2.2. Debug mode
D.2.3. Performance counters
D.2.4. Coprocessors
D.2.5. Debug handler firmware support
D.2.6. Summary
E. CP15 Register Mapping
E.1. About register mapping
E.2. ARM710T processor registers
E.3. ARM720T processor registers
E.4. ARM740T processor registers
E.5. ARM920T and ARM922T processor registers
E.6. ARM925T processor registers
E.7. ARM926EJ-S processor registers
E.8. ARM940T processor registers
E.9. ARM946E-S processor registers
E.10. ARM1020T and ARM10200T processor registers
E.11. XScale microarchitecture processorregisters
F. JTAG Interface Connections
F.1. Multi-ICE JTAG interface connections
F.1.1. JTAG pinouts
F.2. Multi-ICE JTAG port timing characteristics
F.3. TCK frequencies
F.4. TCK values
G. User I/O Connections
G.1. Multi-ICE user I/O pin connections
G.1.1. User input/output pin connections
G.1.2. Input bit logic

List of Figures

1. Key to timing diagram conventions
1.1. The Multi-ICE interface unit
1.2. Connecting multiple debuggers andmultiple targets
2.1. The Multi-ICE product kit
2.2. Multi-ICE interface unit cable connection
2.3. Location of jumper J8
2.4. Multi-ICE current consumption withvoltage
2.5. Start menu items for Multi-ICE
2.6. Unconfigured Multi-ICE server window
2.7. Multi-ICE server window configuredfor an ARM7TDMI
3.1. Multi-ICE server menu items
3.2. The File menu
3.3. The View menu
3.4. The Run Control menu
3.5. The Connection menu
3.6. The Settings menu
3.7. The Help menu
3.8. Autoconfiguring an ARM940T
3.9. TAP driver status dialog
3.10. TAP Controller Device ID registerformat
3.11. The Start-up Options dialog
3.12. The Port Settings dialog
3.13. The User Output Bits dialog
3.14. Status of the user input bits
3.15. The JTAG Settings dialog
3.16. Setting up interaction between devices
3.17. Cascade operation
3.18. Setting up the poll frequency
4.1. The AXD Options menu
4.2. The AXD Choose Target dialog
4.3. Selecting the Multi-ICE DLL usingAXD
4.4. The ADW and ADU Options menu
4.5. ADW configuration dialog with Multi-ICEactive
4.6. Selecting the Multi-ICE DLL usingADW
4.7. Multi-ICE Configuration dialog
4.8. Multi-ICE Welcome dialog
4.9. Driver Details dialog
4.10. Server Browse dialog
4.11. Multi-ICE Processor Settings tabshowing cache setting
4.12. Multi-ICE Processor Settings tabshowing XScale settings
4.13. Multi-ICE Advanced settings tab
4.14. Board tab
4.15. Trace configuration tab
4.16. About tab
4.17. Channel viewer controls
4.18. Saving a named target configuration
4.19. Configuring AXD to run a configurationscript
4.20. Three AXDs and the Multi-ICE serverconfigured for a multiple processor target
4.21. Relating top_of_memory to singlesection program layout
4.22. Register view showing EmbeddedICElogic registers
4.23. The View Registers menu
4.24. The Display Co-processor Regs dialog
4.25. EmbeddedICE logic registers in theRaw Co-processor 0 view
6.1. Basic JTAG port synchronizer
6.2. Timing diagram for the Basic JTAGsynchronizer in Figure 6.1
6.3. JTAG port synchronizer for singlerising-edge D-type ASIC design rules
6.4. Timing diagram for the D-type JTAGsynchronizer in Figure 6.3
6.5. Example reset circuit logic
6.6. Example reset circuit using powersupply monitor ICs
6.7. TAP Controllers serially chainedin an ASIC
6.8. Typical PCB connections
6.9. Target interface voltage levels
F.1. JTAG pin connections, top view
F.2. Multi-ICE JTAG port timing diagram
G.1. User I/O pin connections
G.2. Converting user-input signals toTTL levels

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksowned by ARM Limited. Other brands and names mentioned herein maybe the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.


This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Conformance Notices

This section contains ElectroMagnetic Conformity (EMC)notices and other important notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt frompart 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

This equipment has been tested according to ISE/IEC Guide 22and EN 45014. It conforms to the following product EMC specifications:

The product herewith complies with the requirements of EMCDirective 89/336/EEC as amended.

Revision History
Revision A June1998 First release
Revision B November1998 Internal release
Revision C December1998 Updated for Multi-ICE Release 1.3
Revision D January2001 Updated for Multi-ICE Version 2.0
Revision E September2001 Updated for Multi-ICE Version 2.1
Revision F February2002 Updated for Multi-ICE Version 2.2
Copyright © 1998-2002 ARM Limited. All rights reserved. ARM DUI 0048F