Define the starting addresses and sizes of protection regions, and enable them. To do this, write to coprocessor register c6 in CP15, the system control coprocessor (see Setting protection region addresses and sizes, and enabling each region).

Set the cacheable and bufferable attributes for each region. To do this, write to CP15 registers c2 and c3 (see Setting region cacheable and bufferable flags).

Set access permissions for each region. To do this, write to CP15 register c5 (see Setting region access permissions).

Enable the caches and enable the PU. To do this, write to CP15 register c1 (see Configuring core operation).