ARM® Developer Suite Developer Guide 3.2.4. ARM architecture v5T

In ARM architecture v5T and above:

There are two additional interworking instructions available:
BLX address
The processor performs a pc-relative branch to address with link and changes state. address must be within 32MB of the pc in ARM code, or within 4MB of the pc in Thumb code.
BLX register
The processor performs a branch with link to an address contained in the specified register. The value of bit[0] determines the new processor state.
In either case, bit[0] of lr is set to the current value of the Thumb bit in the CPSR. The means that the return instruction can automatically return to the correct processor state.
If LDR, LDM, or POP load to the pc, they set the Thumb bit in the CPSR to bit[0] of the value loaded to the pc. You can use this to change instruction sets. This is particularly useful for returning from subroutines. The same return instruction can return to either an ARM or Thumb caller.

For more information, see ADS Assembler Guide and ARM Architecture Reference Manual.

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