When the SWI handler is entered, it must establish which SWI is being called. This information can be stored in bits 0-23 of the instruction itself, as shown in Figure 5.1, or passed in an integer register, usually one of r0-r3.

The top-level SWI handler can load the SWI instruction relative to the link register (LDR swi, [lr, #-4]). Do this in assembly language, or C/C++ inline assembler.

The handler must first load the SWI instruction that caused the exception into a register. At this point, lr_SVC holds the address of the instruction that follows the SWI instruction, so the SWI is loaded into the register (in this case r0) using:

    LDR r0, [lr,#-4]

The handler can then examine the comment field bits, to determine the required operation. The SWI number is extracted by clearing the top eight bits of the opcode:

    BIC r0, r0, #0xFF000000

Example 5.5 shows how you can put these instructions together to form a top-level SWI handler.

See Determining the processor state for an example of a handler that deals with both ARM-state and Thumb-state SWI instructions.

    AREA TopLevelSwi, CODE, READONLY  ; Name this block of code.
    EXPORT     SWI_Handler
SWI_Handler
    STMFD      sp!,{r0-r12,lr}        ; Store registers.
    LDR        r0,[lr,#-4]            ; Calculate address of SWI instruction and load it into r0.
    BIC        r0,r0,#0xff000000      ; Mask off top 8 bits of instruction to give SWI number.
    ;
    ; Use value in r0 to determine which SWI routine to execute.
    ;
    LDMFD        sp!, {r0-r12,pc}^    ; Restore registers and return.
    END                               ; Mark end of this file.