ARM ® DeveloperSuite Developer Guide

Version 1.2

Table of Contents

About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback on the ARM Developer Suite
Feedback on this book
1. Introduction
1.1. About the ARM Developer Guide
1.1.1. Example code
1.2. General programing issues
1.3. Developing for the ARM
1.3.1. Using the Procedure call standards
1.3.2. Interworking ARM and Thumb code
1.3.3. Mixing C, C++, and Assembly Language
1.3.4. Handling Processor Exceptions
1.3.5. Writing Code for ROM
1.3.6. Caches and tightly coupled memory
1.3.7. Using the Debug Communications Channel
2. Using the Procedure Call Standard
2.1. About the ARM-Thumb Procedure CallStandard
2.1.1. ATPCS variants
2.1.2. ARM C libraries
2.1.3. Conformance to the ATPCS
2.1.4. Processes and the memory model
2.2. Register roles andnames
2.2.1. Register roles
2.2.2. Register names
2.3. The stack
2.3.1. Stack terminology
2.3.2. Stack unwinding
2.3.3. Eight-byte alignment
2.4. Parameter passing
2.4.1. Nonvariadic routines
2.4.2. Variadic routines
2.4.3. Result return
2.5. Stack limit checking
2.5.1. Rules for stack limit checked code
2.5.2. Register usage with stack limit checking
2.5.3. Stack checking in C and C++
2.5.4. Stack checking in assemblylanguage
2.6. Read-only position independence
2.6.1. Register usage with ROPI
2.6.2. Writing code for ROPI
2.7. Read-write position independence
2.7.1. Reentrant routines
2.7.2. Register usage with RWPI
2.7.3. Position-independent data addressing
2.7.4. Writing assembly language for RWPI
2.8. Interworking between ARM and Thumbstates
2.8.1. Register usage with interworking
2.9. Floating-point options
2.9.1. The VFP architecture
2.9.2. The FPA architecture
2.9.3. No floating-point hardware
2.9.4. softVFP+VFP
3. Interworking ARM and Thumb
3.1. About interworking
3.1.1. When to use interworking
3.1.2. Using the /interworkoption
3.1.3. Detecting interworking calls
3.2. Assembly language interworking
3.2.1. The branch and exchangeinstruction
3.2.2. Changing the assemblermode
3.2.3. Example ARM header
3.2.4. ARM architecture v5T
3.2.5. Labels in Thumb code
3.3. C and C++ interworking and veneers
3.3.1. Compiling code for interworking
3.3.2. Basic rules for interworking
3.3.3. Using two copies of the same function
3.4. Assembly language interworking usingveneers
3.4.1. Assembly-only interworking using veneers
3.4.2. C, C++, and assembly language interworking using veneers
4. Mixing C, C++, and Assembly Language
4.1. Using the inline assemblers
4.1.1. Invoking the inline assembler
4.1.2. ARM and Thumb instruction sets
4.1.3. Differences between the inline assemblersand armasm
4.1.4. Usage
4.1.5. Examples
4.2. Accessing C global variables fromassembly code
4.3. Using C header files from C++
4.3.1. Including system C header files
4.3.2. Including your own C header files
4.4. Calling between C, C++, and ARM assemblylanguage
4.4.1. General rules for calling between languages
4.4.2. Information specific to C++
4.4.3. Examples
5. Handling Processor Exceptions
5.1. About processor exceptions
5.1.1. The vector table
5.1.2. Use of modes and registers by exceptions
5.1.3. Exception priorities
5.2. Entering and leaving an exception
5.2.1. The processor response to an exception
5.2.2. Returning from an exception handler
5.2.3. The return addressand return instruction
5.3. Installing an exception handler
5.3.1. Installing the handlers at reset
5.3.2. Installing the handlersfrom C
5.4. SWI handlers
5.4.1. SWI handlers in assembly language
5.4.2. SWI handlers in C and assembly language
5.4.3. Using SWIs in Supervisormode
5.4.4. Calling SWIs from an application
5.4.5. Calling SWIs dynamically from an application
5.5. Interrupt handlers
5.5.1. Simple interrupt handlers in C
5.5.2. Reentrant interrupt handlers
5.5.3. Example interrupt handlers in assemblylanguage
5.6. Reset handlers
5.7. Undefined Instruction handlers
5.8. Prefetch Abort handler
5.9. Data Abort handler
5.10. Chaining exception handlers
5.10.1. A single extended handler
5.10.2. Several chained handlers
5.11. Handling exceptions on Thumb-capableprocessors
5.11.1. Thumb processor response to an exception
5.11.2. The return address
5.11.3. Determining the processor state
5.12. System mode
6. Writing Code for ROM
6.1. About writing code for ROM
6.2. Memory map considerations
6.2.1. ROM at 0x0
6.2.2. RAM at 0x0
6.3. Initializing the system
6.3.1. Initializing the execution environment
6.3.2. Initializing the application
6.4. The reference C example using semihosting
6.4.1. Memory map
6.4.2. Sample code
6.5. Loading the ROM image at address 0
6.5.1. Memory map
6.5.2. Scatter-load description file
6.5.3. Sample code
6.5.4. Building the example
6.6. Using both scatter loading and remapping
6.6.1. Memory map
6.6.2. Scatter-load description file
6.6.3. Initialization code
6.6.4. Building the example
6.6.5. Additional examples of remapping
6.7. A semihosted application with interrupthandling
6.7.1. Memory map
6.7.2. Building the example
6.7.3. Sample code
6.8. An embeddable application with interrupthandling
6.8.1. Memory map
6.8.2. Building the example
6.8.3. Scatter-load description file
6.8.4. Sample code
6.9. Using scatter loading with memory-mappedI/O
6.9.1. Using pointers to access I/O
6.9.2. Using unions
6.9.3. Using arrays or structs
6.9.4. Using scatter loading
6.9.5. Code efficiency
6.10. Troubleshooting
6.10.1. Linker error __semihosting_swi_guard
6.10.2. Setting $top_of_memory
6.10.3. Vector table code eliminated
6.10.4. Errors with scatter-loading descriptionfiles
6.11. Measuring code and data size
6.11.1. Interpreting size information
6.11.2. Calculating ROM and RAM requirements
7. Caches and Tightly Coupled Memories
7.1. About caches and tightly coupled memory
7.1.1. About caches
7.1.2. About tightly coupled memory
7.1.3. Models of caches and tightly coupledmemory
7.1.4. Cache performance
7.2. System control coprocessor
7.3. Memory protection units
7.3.1. Harvard architecture
7.3.2. Von Neumann architecture
7.3.3. Overlapping regions
7.4. Configuring a PU
7.4.1. Setting protectionregion addresses and sizes, and enabling each region
7.4.2. Setting region cacheableand bufferable flags
7.4.3. Setting region accesspermissions
7.4.4. Configuring core operation
7.5. Memory management units
7.5.1. Virtual to physical address mapping
7.5.2. Memory access permissionsand domains
7.5.3. Cacheable and bufferableflags
7.6. Configuring an MMU
7.6.1. Altering the translation table during program execution
7.6.2. Building the translationtable
7.6.3. Setting the location of the translationtable
7.6.4. Aliasing a region
7.6.5. Configuring core operation
7.7. Tightly coupled memory
7.7.1. ARM966E-S memory map
7.7.2. Initializing the ARM966E-S
7.7.3. ARM966E-S warm reset
7.7.4. ARM966E-S performance issues
8. Debug Communications Channel
8.1. About the Debug Communications Channel
8.2. Command-line debugging commands
8.3. Enabling comms channel viewing
8.3.1. Comms channel viewing in AXD
8.4. Target transfer of data
8.5. Polled debug communications
8.5.1. Viewing EmbeddedICE logic registers
8.5.2. Target to debugger communication
8.5.3. Debugger to target communication
8.6. Interrupt-driven debug communications
8.7. Access from Thumb state
8.8. Semihosting

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksowned by ARM Limited. Other brands and names mentioned herein maybe the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

Revision History
Revision A October1999 Release 1.0
Revision B March2000 Release 1.0.1
Revision C November2000 Release 1.1
Revision D November2001 Release 1.2
Copyright © 1999-2001 ARM Limited. All rights reserved. ARM DUI 0056D