4.16.1. Interrupt controller

The base address of the interrupt controller, IntBase, is configurable (see Interrupt controller).

Table 4.10 shows the location of individual registers.

Table 4.10. Interrupt controller memory map

AddressReadWrite
IntBaseIRQStatusReserved
IntBase + 004IRQRawStatusReserved
IntBase + 008IRQEnableIRQEnableSet
IntBase + 00CReservedIRQEnableClear
IntBase + 010ReservedIRQSoft
IntBase + 100FIQStatusReserved
IntBase + 104FIQRawStatusReserved
IntBase + 108FIQEnableFIQEnableSet
IntBase + 10CReservedFIQEnableClear

Interrupt controller defined bits

The FIQ interrupt controller is one bit wide. It is located on bit 0.

Table 4.11 gives details of the interrupt sources associated with bits 1 to 5 in the IRQ interrupt controller registers. You can use bit 0 for a duplicate FIQ input.

Table 4.11. Interrupt sources

BitInterrupt source
0FIQ source
1Programmed interrupt
2Communications channel Rx
3Communications channel Tx
4Timer 1
5Timer 2

Note

Timer 1 and Timer 2 can be configured to use different bits in the IRQ controller registers, see Timer.

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