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Home > ARMulator Basics > Tracer > Interpreting trace file output |
This section describes how you interpret the output from Tracer.
The following example shows part of a trace file:
Date: Thu Aug 9 16:41:36 2001
Source: Armul
Options: Trace Instructions (Disassemble) Trace Memory Cycles
BNR4O___ A0000000 00000C1E
BNR8O___ 00008000 E28F8090 E898000F
BSR8O___ 00008008 E0800008 E0811008
BSR8O___ 00008010 E0822008 E0833008
BSR8O___ 00008018 E240B001 E242C001
MNR4O___ 00008000 E28F8090
IT 00008000 e28f8090 ADD r8,pc,#0x90 ; #0x8098
MNR4O___ 00008004 E898000F
IT 00008004 e898000f LDMIA r8,{r0-r3}
BNR4O___ A0000000 00000C1E
BNR8O___ 00008098 00007804 00007828
BSR8O___ 00008080 10844009 E3C44003
BSR8O___ 00008088 E2555004 24847004
BSR8O___ 00008090 8AFFFFFC EAFFFFF2
MNR8____ 00008098 00007804 00007828
BNR8O___ 000080A0 00007828 00007840
BSR8O___ 000080A8 E3A00840 E1A0F00E
BSR8O___ 000080B0 E92D400C E28F0014
BSR8O___ 000080B8 E5901000 E5900004
MNR8____ 000080A0 00007828 00007840
MNR4O___ 00008008 E0800008
IT 00008008 e0800008 ADD r0,r0,r8
MNR4O___ 0000800C E0811008
IT 0000800C e0811008 ADD r1,r1,r8
MNR4O___ 00008010 E0822008
In a trace file, there can be five types of line:
M lines indicate:
memory accesses, for cores without on-chip memory
on-chip memory accesses, for cores with on-chip memory.
They have the following format for general memory accesses:
M<type><rw><size>[O][L][S] <address> <data>
where:
<type>
indicates the cycle type:
S
sequential
N
nonsequential.
<rw>
indicates either a read or a write operation:
R
read
W
write.
<size>
indicates the size of the memory access:
4
word (32 bits)
2
halfword (16 bits)
1
byte (8 bits).
O
indicates an opcode fetch (instruction fetch).
L
indicates
a locked access (SWP
instruction).
S
indicates a speculative instruction fetch.
<address>
gives the address in hexadecimal format, for example 00008008
.
<data>
can show one of the following:
value
gives the read/written value, for example EB00000C
(wait)
indicates nWAIT was LOW to insert a wait state
(abort)
indicates ABORT was HIGH to abort the access.
Trace memory lines can also have any of the following formats:
MI
for idle cycles
MC
for coprocessor cycles
MIO
for idle cycles on the instruction bus of Harvard architecture processors such as ARM9TDMI™.
The format of the trace instruction (I) lines is as follows:
[ IT | IS ] <instr_addr> <opcode> [<disassembly>]
For example:
IT 00008044 e04ec00f SUB r12,r14,pc
where:
IT
indicates that the instruction was taken.
IS
indicates that the instruction was skipped (almost all ARM instructions are conditional).
<instr_addr>
shows the address of the instruction in hexadecimal format,
for example 00008044
.
<opcode>
gives
the opcode in hexadecimal format, for example e04ec00f
.
<disassembly>
gives the disassembly (uppercase if the instruction is taken),
for example, SUB r12,r14,pc
. This is optional
and is enabled by setting Disassemble=True
in peripherals.ami
.
Branches with link in Thumb code appear as two entries, with the first marked:
1st instr of BL pair.
The format of the event (E) lines is as follows:
E <word1> <word2> <event_number>
For example:
E 00000048 00000000 10005
where:
<word1>
gives the first of a pair of words, such as the pc value.
<word2>
gives the second of a pair of words, such as the aborting address.
<event_number>
gives an event number, for example 0x10005.
This
is MMU Event_ITLBWalk
. Events are described in Events.
The format of the event (R) lines is as follows:
R <register>=<newvalue>[,<anotherregister>=<newvalue>[...]]
For example:
R r14=20000060, cpsr=200000d3
where:
<register>
is a register that has a new value as a result of the current instruction
<newvalue>
is the new contents of <register>
.