2.5.3. Cached cores with MMUs or PUs and AMBA ASB interfaces

Table 2.3 shows the meanings of the bus cycle types for cached cores with AMBA ASB interfaces. For additional cycle types for these cores, see Internal cycle types for cached cores.

ARM920T, for example, is a cached core with an MMU. ARM940T is an example of a cached core with a PU.

Table 2.3. Cycle type meanings for cached cores with AMBA ASB interfaces

Cycle typesMeaning
A_CyclesAn address is published speculatively. No data is transferred. Listed as I_Cycles in $statistics.
S_CyclesSequential data is transferred from the current address.

There are no N_Cycles for these cores. Nonsequential accesses use an A_Cycle followed by an S_Cycle. This is the same as a merged I-S cycle.

Copyright © 1999-2001 ARM Limited. All rights reserved.ARM DUI0058D
Non-Confidential