2.5.4. Cached cores with MMUs or PUs and AMBA AHB interfaces

Table 2.4 shows the types of transfer that can occur on the Advanced High-speed Bus (AHB). ARM946E-S, for example, is a cached core with an AHB interface. For additional cycle types for these cores, see Internal cycle types for cached cores.

Table 2.4. Cycle types on AMBA AHB interfaces

Cycle typesMeaning
IDLEThe bus master does not want to use the bus. Slaves must respond with a zero wait state OKAY response on HRESP.
BUSYThe bus master is in the middle of a burst, but cannot proceed to the next sequential access. Slaves must respond with a zero wait state OKAY response on HRESP.
NON-SEQThe start of a burst or single access. The address is unrelated to the address of the previous access.
SEQContinuing with a burst. The address is equal to the previous address plus the data size.

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