2.5.2. Uncached Harvard cores

Table 2.2 shows the meanings of cycle types for uncached Harvard cores. ARM9TDMI, for example, is an uncached Harvard core.

Table 2.2. Cycle type meanings for uncached Harvard cores

Cycle typesInstruction busData busMeaning
Core cycles--The total number of ticks of the core clock. This includes pipeline stalls due to interlocks and instructions that take more than one cycle.
ID_CyclesActiveActive-
I_CyclesActiveIdle-
Idle CyclesIdleIdle-
D_CyclesIdleActive-
Total--The sum of core cycles, ID_Cycles, I_Cycles, Idle_Cycles, D_Cycles, and Waits.

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