4.16.2. Timer

The base address of the timer, TimerBase, is configurable (see Timer).

See Table 4.12 for the location of individual registers.

Table 4.12. Timer memory map

TimerBase + 04Timer1ValueReserved
TimerBase + 08Timer1ControlTimer1Control
TimerBase + 0CReservedTimer1Clear
TimerBase + 10ReservedReserved
TimerBase + 20Timer2LoadTimer2Load
TimerBase + 24Timer2ValueReserved
TimerBase + 28Timer2ControlTimer2Control
TimerBase + 2CReservedTimer2Clear
TimerBase + 30ReservedReserved

Timer load registers

Write a value to one of these registers to set the initial value of the corresponding timer counter. You must write the top 16 bits as zeroes.

If the timer is in periodic mode, this value is also reloaded to the timer counter when the counter reaches zero.

If you read from this register, the bottom 16 bits return the value that you wrote. The top 16 bits are undefined.

Timer value registers

Timer value registers are read-only. The bottom 16 bits give the current value of the timer counter. The top 16 bits are undefined.

Timer clear registers

Timer clear registers are write-only. Writing to one of them clears an interrupt generated by the corresponding timer.

Timer control registers

See Table 4.14 and Table 4.13 for details of timer register bits. Only bits 7, 6, 3, and 2 are used. You must write all others as zeroes.

Table 4.13. Clock prescaling using bits 2 and 3

Bit 3Bit 2Clock divided byStages of prescale

The counter counts downwards. It counts BCLK cycles, or BCLK cycles divided by 16 or 256. Bits 2 and 3 define the prescaling applied to the clock.

Table 4.14. Timer enable and mode control using bits 6 and 7

Bit 7Timer disabledTimer enabled
Bit 6Free-running modePeriodic mode

In free-running mode, the timer counter overflows when it reaches zero, and continues to count down from 0xFFFF.

In periodic mode, the timer generates an interrupt when the counter reaches zero. It then reloads the value from the load register and continues to count down from this value.

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