2.6.4. Memory regions

The rest of the Pagetables configuration section defines a set of memory regions. Each region has its own set of properties.

By default, peripherals.ami contains a description of a two regions:


{ Region[0]
VirtualBase=0
PhysicalBase=0
Size=4GB
Cacheable=No
Bufferable=No
Updateable=Yes
Domain=0
AccessPermissions=3
Translate=Yes
}
{ Region[1]
VirtualBase=0
PhysicalBase=0
Size=128Mb
Cacheable=Yes
Bufferable=Yes
Updateable=Yes
Domain=0
AccessPermissions=3
Translate=Yes
}

You can add more regions following the same general form:

Region[n]

names the regions, starting with Region[0]. n is an integer.

VirtualBase

applies only to a processor with an MMU. It gives the address of the base of the region in the virtual address space of the processor. This address must be aligned to a 1MB boundary. It is mapped to PhysicalBase by the MMU.

PhysicalBase

gives the physical address of the base of the region. On a processor with an MMU, this address must be aligned to a 1MB boundary.

On a processor with a PU it must be aligned to a boundary that is a multiple of the size of the region.

Size

specifies the size of this region. On a processor with an MMU Size must be a whole number of megabytes. On a processor with a PU, Size must be 4KB or a power-of-two multiple of 4KB.

Cacheable

specifies whether the region is to be marked as cacheable. If it is, reads from the region will be cached.

Bufferable

specifies whether the region is to be marked as bufferable. If it is, writes to the region will use the write buffer.

Updateable

applies only to the ARM610™ processor. It controls the U bit in the translation table entry.

Domain

applies only to processors with an MMU. It specifies the domain field of the table entry.

AccessPermissions

specifies the access controls to the region. Refer to the processor technical reference manual for further information.

Translate

controls whether accesses to this region cause translation faults. Setting Translate=No for a region causes an abort to occur whenever the processor reads from or writes to that region.

You must ensure that you do not define more regions than your target hardware supports. At least one region must be defined.

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