ARM® Developer Suite Debug Target Guide 2.6.5. Pagetable module and memory management units

2.6.5. Pagetable module and memory management units

Processors such as ARM720T™ and ARM920T™ have an MMU.

An MMU uses a set of page tables, stored in memory, to define memory regions. On reset, the pagetable module writes out a top-level page table to the address specified in the translation table base register. The table corresponds to the regions you define in the Pagetables section of peripherals.ami.

For example, the default configuration details, given in Memory regions, define the following page table:

The entire address space, 4GB, is defined as a single region. This region is not cacheable or bufferable. Virtual addresses are mapped directly to the same physical addresses over the whole address space.
The first 128MB of the address space is defined as a second region overlapping the first. This region is cacheable and bufferable. Virtual addresses are mapped directly to physical addresses.

They also set up the control registers as follows:

The translation table base register, register 2, is initialized to point to this page table in memory, at 0xA0000000.
The domain access control register, register 3, is initialized with value 0x00000001. This sets the access to the region as client.
The M, C and W bits of the control register, register 1, are configured to enable the MMU, cache, and write buffer. If the processor has separate instruction and data caches, the I bit configures the instruction cache enabled.

Copyright © 1999-2001 ARM Limited. All rights reserved.	ARM DUI0058D
Non-Confidential
PDF version