2.6.2. Controlling the MMU or PU and cache

The first set of flags enables or disables features of the caches and MMU or PU:


MMU=Yes
AlignFaults=No
Cache=Yes
WriteBuffer=Yes
Prog32=Yes
Data32=Yes
LateAbort=Yes
BigEnd=No
BranchPredict=Yes
ICache=Yes
HighExceptionVectors=No
FastBus=No

Each flag corresponds to a bit in the system control register, c1 of CP15.

Some flags only apply to certain processors. For example:

These flags are ignored by other processor models.

The FastBus flag is used by some cores such as ARM940T. Refer the technical reference manual for your core. If your system uses FastBus Mode, set FastBus=Yes for benchmarking. If set FastBus=No, ARMulator assumes that the memory clock is slower than the core clock by a factor of MCCFG. ARMulator does not model Asynchronous mode.

The MMU flag is used to enable the PU in processors with a PU.

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