4.13.1. Format of a map file

The format of each line is:

start size name width access{*} read-times write-times



is the start address of the memory region in hexadecimal,for example 80000.


is the size of the memory region in hexadecimal, for example, 4000.


is a single word that you can use to identify the memory region when memory access statistics are displayed. You can use any name. To ease readability of the memory access statistics, give a descriptive name such as SRAM, DRAM, or EPROM.


is the width of the data bus in bytes (that is, 1 for an 8-bit bus, 2 for a 16-bit bus, or 4 for a 32-bit bus).


describes the type of accesses that can be performed on this region of memory:


for read-only.


for write-only.


for read-write.


for no access. Any access causes a Data or Prefetch Abort.

An asterisk (*) can be appended to access to describe a Thumb-based system that uses a 32-bit data bus to memory, but which has a 16-bit latch to latch the upper 16 bits of data, so that a subsequent 16-bit sequential access can be fetched directly out of the latch.


describes the nonsequential and sequential read times in nanoseconds. These must be entered as the nonsequential read access time followed by a slash ( / ), followed by the sequential read access time. Omitting the slash and using only one figure indicates that the nonsequential and sequential access times are the same.


For accurate modelling of real devices, you might have to add a signal propagation delay (20 to 30ns) to the read and write times quoted for a memory chip.


describes the nonsequential and sequential write times. The format is the same as that given for read times.

The following examples assume a clock speed of 20MHz, the default.

Example 1

0 80000000 RAM 4 rw 135/85 135/85

This describes a system with a single continuous section of RAM from 0 to 0x7FFFFFFF with a 32-bit data bus, read-write access, nonsequential access time of 135ns, and sequential access time of 85ns.

Example 2

This example describes a typical embedded system with 32KB of on-chip memory, 16-bit ROM and 32KB of external DRAM:

00000000 8000 SRAM  4 rw   1/1     1/1
00008000 8000 ROM   2 r  100/100 100/100
00010000 8000 DRAM  2 rw 150/100 150/100
7FFF8000 8000 Stack 2 rw 150/100 150/100

There are four regions of memory:

  • A fast region from 0 to 0x7FFF with a 32-bit data bus. This is labeled SRAM.

  • A slower region from 0x8000 to 0xFFFF with a 16-bit data bus. This is labelled ROM and contains the image code. It is marked as read-only.

  • A region of RAM from 0x10000 to 0x17FFF that is used for image data.

  • A region of RAM from 0x7FFF8000 to 0x7FFFFFFF that is used for stack data. The stack pointer is initialized to 0x80000000.

In the final hardware, the two distinct regions of the external DRAM are combined. This does not make any difference to the accuracy of the simulation.

To represent fast (no wait state) memory, the SRAM region is given access times of 1ns. In effect, this means that each access takes 1 clock cycle, because ARMulator rounds this up to the nearest clock cycle. However, specifying it as 1ns allows the same map file to be used for a number of simulations with differing clock speeds.


To ensure accurate simulations, make sure that all areas of memory likely to be accessed by the image you are simulating are described in the memory map.

To ensure that you have described all areas of memory that you think the image accesses, you can define a single memory region that covers the entire address range as the last line of the map file. For example, you could add the following line to the above description:

00000000 80000000 Dummy 4 - 1/1 1/1

You can then detect if any reads or writes are occurring outside the regions of memory you expect using the print $memory_statistics command.


A dummy memory region must be the last entry in a map file.

Reading the memory statistics

To read the memory statistics use the command:

print $memory_statistics

print $memstats is a short version of print $memory_statistics.

Example 4.1 shows the form of reports given.

Example 4.1. 

address  name    W acc R(N/S)  W(N/S)    reads(N/S)   writes(N/S)  time (ns)
00000000 Dummy   4 -     1/1     1/1        0/0           0/0      0
7FFF8000 Stack   2 rw  150/100 150/100   9290/10590    4542/11688  8538300
00010000 DRAM    2 rw  150/100 150/100  18817/18      11031/140    8915800
00008000 ROM     2 r   100/100 100/100  48638/176292      0/0      44817000
00000000 SRAM    4 rw    1/1     1/1        0/0           0/0     0

The report in Example 4.1 shows that:

  • ROM access is critical to this application. Consider using faster ROM, using burst-capable ROM, or making the ROM wider (32 bits).

  • No use was made of SRAM at 0x0. Consider locating the stack, or other data at 0x0.

Copyright © 1999-2001 ARM Limited. All rights reserved.ARM DUI0058D