| CP15: ID | Chip ID | CP = 15: CRn = 0, CRm = 0, op_1 = 0, op_2 =
0 |
| CP15: Type | Cache type | CP = 15: CRn = 0, CRm = 0, op_1 = 0, op_2 =
1 |
| CP15: Control | Control | CP = 15: CRn = 1, CRm = 0, op_1 = 0, op_2 =
0 |
| CP15: TTBR | Translation table base register | CP = 15: CRn = 2, CRm = 0, op_1 = 0, op_2 =
0 |
| CP15: DACR | Domain access control register | CP = 15: CRn = 3, CRm = 0, op_1 = 0, op_2 =
0 |
| CP15: FSR | Fault status register | CP = 15: CRn = 5, CRm = 0, op_1 = 0, op_2 =
0 |
| CP15: DFAR | Fault address register | CP = 15: CRn = 6, CRm = 0, op_1 = 0, op_2 =
0 |
| CP15: IFAR | Fault address register | CP = 15: CRn = 6, CRm = 0, op_1 = 0, op_2 =
1 |
| CP15: DLOCK | Data cache lockdown | CP = 15: CRn = 9, CRm = 0, op_1 = 0, op_2 =
0 |
| CP15: ILOCK | Instruction cache lockdown | CP = 15: CRn = 9, CRm = 0, op_1 = 0, op_2 =
1 |
| CP15: TLBDLOCK | Data TLB lockdown | CP = 15: CRn = 10, CRm = 0, op_1 = 0, op_2 =
0 |
| CP15: TLBILOCK | Instruction TLB lockdown | CP = 15: CRn = 10, CRm = 0, op_1 = 0, op_2 =
1 |
| CP15: PID | Process ID register | CP = 15: CRn = 13, CRm = 0, op_1 = 0, op_2 =
0 |
| CP15: Cache operations: Invalidate | Invalidate both caches | CP = 15: CRn = 7, CRm = 7, op_1 = 0, op_2 =
0 |
| CP15: Cache operations: Invalidate_I | Invalidate entire I cache | CP = 15: CRn = 7, CRm = 5, op_1 = 0, op_2 =
0 |
| CP15: Cache operations: Invalidate_I_Address | Invalidate I cache single entry (by address) | CP = 15: CRn = 7, CRm = 5, op_1 = 0, op_2 =
1 |
| CP15: Cache operations: Prefetch_I | Prefetch I cache line | CP = 15: CRn = 7, CRm = 13, op_1 = 0, op_2 =
1 |
| CP15: Cache operations: Invalidate_D | Invalidate entire D cache | CP = 15: CRn = 7, CRm = 6, op_1 = 0, op_2 =
0 |
| CP15: Cache operations: Invalidate_D_Address | Invalidate D cache single entry (by address) | CP = 15: CRn = 7, CRm = 6, op_1 = 0, op_2 =
1 |
| CP15: Cache operations: Clean_D_Address | Clean D cache single entry (by address) | CP = 15: CRn = 7, CRm = 10, op_1 = 0, op_2 =
1 |
| CP15: Cache operations: CleanInvalidate_D_Address | Clean and invalidate D cache single entry (by
address) | CP = 15: CRn = 7, CRm = 14, op_1 = 0, op_2 =
1 |
| CP15: Cache operations: Clean_D_Index | Clean D cache single index | CP = 15: CRn = 7, CRm = 10, op_1 = 0, op_2 =
2 |
| CP15: Cache operations: CleanInvalidate_D_Index | Clean and invalidate D cache single index | CP = 15: CRn = 7, CRm = 14, op_1 = 0, op_2 =
2 |
| CP15: Cache operations: Drain | Drain write buffer | CP = 15: CRn = 7, CRm = 10, op_1 = 0, op_2 =
4 |
| CP15: Cache operations: Wait | Wait for interrupt | CP = 15: CRn = 7, CRm = 0, op_1 = 0, op_2 =
4 |
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