5.1.1. LDR and STR, immediate offset

Load Register and Store Register. Address in memory specified as an immediate offset from a value in a register.


op Rd, [Rn, #immed_5x4]
opH Rd, [Rn, #immed_5x2]
opB Rd, [Rn, #immed_5x1]



is either:


Load register


Store register.


is a parameter specifying an unsigned halfword transfer.


is a parameter specifying an unsigned byte transfer.


is the register to be loaded or stored. Rd mustbe in the range r0-r7.


is the register containing the base address. Rn must be in the range r0-r7.


is the offset. It is an expression evaluating (at assembly time) to a multiple of N in the range 0-31N.


STR instructions store a word, halfword, or byte to memory.

LDR instructions load a word, halfword, or byte from memory.

The address is found by adding the offset to the base address from Rn.

Immediate offset halfword and byte loads are unsigned. The data is loaded into the least significant word or byte of Rd, and the rest of Rd is filled with zeroes.

Address alignment for word and halfword transfers

The address must be divisible by 4 for word transfers, and by 2 for halfword transfers.

If your system has a system coprocessor (cp15), you can enable alignment checking. Non-aligned transfers cause an alignment exception if alignment checking is enabled.

If your system does not have a system coprocessor (cp15), or alignment checking is disabled:

  • A non-aligned load corrupts Rd.

  • A non-aligned save corrupts two or four bytes in memory. The corrupted location in memory is [address AND NOT 0x1] for halfword saves, and [address AND NOT 0x3] for word saves.


These instructions are available in all T variants of the ARM architecture.


    LDR     r3,[r5,#0]
    STRB    r0,[r3,#31]
    STRH    r7,[r3,#16]
    LDRB    r2,[r4,#label-{PC}]

Incorrect examples

    LDR     r13,[r5,#40]    ; high registers not allowed
    STRB    r0,[r3,#32]     ; 32 is out of range for byte transfers
    STRH    r7,[r3,#15]     ; offsets for halfword transfers must be even
    LDRH    r6,[r0,#-6]     ; negative offsets not supported
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