5.4.4. BLX

Branch with Link, and optionally exchange instruction set.


BLX label



is an ARM register containing the address to branchto.

Bit 0 of Rm is not used as part of the address. If bit 0 of Rm is clear:

  • Bit 1 must also be clear.

  • The instruction clears the T flag in the CPSR. Code at the destination is interpreted as ARM code.


is a program-relative expression. See Register-relative and program-relative expressions for more information.

BLX label always causes a change to ARM state.


The BLX instruction:

  • copies the address of the next instruction into r14 (lr, the link register)

  • causes a branch to label, or to the address held in Rm

  • changes instruction set to ARM if either:

    • bit 0 of Rm is clear

    • the BLX label form is used.

The machine-level instruction cannot branch to an address outside ±4Mb of the current instruction. When necessary, the ARM linker inserts code (a veneer) to allow longer branches (see The ARM linker chapter in ADS Linker and Utilities Guide).


This instruction is available in all T variants of ARM architecture version 5 and above.


    BLX r6
    BLX armsub
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