5.1.3. LDR and STR, pc or sp relative

Load Register and Store Register. Address in memory specified as an immediate offset from a value in the pc or the sp.


There is no pc-relative STR instruction.


LDR Rd, [pc, #immed_8x4]
LDR Rd, label
LDR Rd, [sp, #immed_8x4]
STR Rd, [sp, #immed_8x4]



is the register to be loaded or stored. Rd mustbe in the range r0 to r7.


is the offset. It is an expression evaluating (at assembly time) to a multiple of 4 in the range 0 to 1020.


is a program-relative expression. See Register-relative and program-relative expressions for more information.

label must be after the current instruction, and within 1KB of it.


STR instructions store a word to memory.

LDR instructions load a word from memory.

The address is found by adding the offset to the base address from pc or sp. Bit[1] of the pc is ignored. This ensures that the address is word-aligned.

Address alignment for word and halfword transfers

The address must be a multiple of 4.

If your system has a system coprocessor (cp15), you can enable alignment checking. Non-aligned transfers cause an alignment exception if alignment checking is enabled.

If your system does not have a system coprocessor (cp15), or alignment checking is disabled:

  • A non-aligned load corrupts Rd.

  • A non-aligned save corrupts four bytes in memory. The corrupted location in memory is [address AND NOT b11].


These instructions are available in all T variants of the ARM architecture.


    LDR     r2,[pc,#1016]
    LDR     r5,localdata
    LDR     r0,[sp,#920]
    STR     r1,[sp,#20]

Incorrect examples

    LDR     r13,[pc,#8]   ; Rd must be in range r0-r7
    STR     r7,[pc,#64]   ; there is no pc-relative STR instruction
    STRH    r0,[sp,#16]   ; there are no pc- or sp-relative
                          ; halfword or byte transfers
    LDR     r2,[pc,#81]   ; immediate must be a multiple of four
    LDR     r1,[pc,#-24]  ; immediate must not be negative
    STR     r1,[sp,#1024] ; maximum immediate value is 1020
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