5.1.2. LDR and STR, register offset

Load Register and Store Register. Address in memory specified as a register-based offset from a value in a register.

Syntax

op Rd, [Rn, Rm]

where:

op

is one of the following:

LDR

Load register, 4-byte word

STR

Store register, 4-byte word

LDRH

Load register, 2-byte unsigned halfword

LDRSH

Load register, 2-byte signed halfword

STRH

Store register, 2-byte halfword

LDRB

Load register, unsigned byte

LDRSB

Load register, signed byte

STRB

Store register, byte.

Note

There is no distinction between signed and unsigned storeinstructions.

Rd

is the register to be loaded or stored. Rd must be in the range r0-r7.

Rn

is the register containing the base address. Rn must be in the range r0-r7.

Rm

is the register containing the offset. Rm must be in the range r0-r7.

Usage

STR instructions store a word, halfword, or byte from Rd to memory.

LDR instructions load a word, halfword, or byte from memory to Rd.

The address is found by adding the offset to the base address from Rn.

Register offset halfword and byte loads can be signed or unsigned. The data is loaded into the least significant word or byte of Rd, and the rest of Rd is filled with zeroes for an unsigned load, or with copies of the sign bit for a signed load.

Address alignment for word and halfword transfers

The address must be divisible by 4 for word transfers, and by 2 for halfword transfers.

If your system has a system coprocessor (cp15), you can enable alignment checking. Non-aligned transfers cause an alignment exception if alignment checking is enabled.

If your system does not have a system coprocessor (cp15), or alignment checking is disabled:

  • A non-aligned load corrupts Rd.

  • A non-aligned save corrupts memory. The corrupted location in memory is the halfword at [address AND NOT 0x1] for halfword saves, and the word at [address AND NOT b11] for word saves.

Architectures

These instructions are available in all T variants of the ARM architecture.

Examples

    LDR     r2,[r1,r5]
    LDRSH   r0,[r0,r6]
    STRB    r1,[r7,r0]

Incorrect examples

    LDR     r13,[r5,r3]   ; high registers not allowed
    STRSH   r7,[r3,r1]    ; no signed store instruction
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