### 5.3.2. ASR, LSL, LSR, and ROR

Shift and rotate operations. These instructions can use a value contained in a register, or an immediate shift value.

#### Syntax

````op` `Rd`, `Rs`
```
````op` `Rd`, `Rm`, #`expr`
```

where:

`op`

is one of:

`ASR`

Arithmetic Shift Right. Register contents are treatedas two’s complement signed integers. The sign bit is copied into vacated bits.

`LSL`

Logical Shift Left. Vacated bits are cleared.

`LSR`

Logical Shift Right. Vacated bits are cleared.

`ROR`

Rotate Right. Bits moved out of the right-hand end of the register are rotated back into the left-hand end.

### Note

`ROR` can only be used with a register-controlled shift.

`Rd`

is the destination register. It is also the source register for register-controlled shifts. `Rd` must be in the range `r0`-`r7`.

`Rs`

is the register containing the shift value for register-controlled shifts. `Rm` must be in the range `r0`-`r7`.

`Rm`

is the source register for immediate shifts. `Rm` must be in the range `r0`-`r7`.

`expr`

is the immediate shift value. It is an expression evaluating (at assembly time) to an integer in the range:

• 0-31 if `op` is `LSL`

• 1-32 otherwise.

#### Register-controlled shift

These instructions take the value from `Rd`, apply the shift to it, and place the result back into `Rd`.

Only the least significant byte of `Rs` is used for the shift value.

For all these instructions except `ROR`:

• if the shift is 32, `Rd` is cleared, and the last bit shifted out remains in the C flag

• if the shift is greater than 32, `Rd` and the C flag are cleared.

#### Immediate shift

These instructions take the value from `Rm`, apply the shift to it, and place the result into `Rd`.

#### Condition flags

These instructions update the N and Z flags according to the result. The V flag is not affected.

The C flag:

• is unaffected if the shift value is zero

• otherwise, contains the last bit shifted out of the source register.

#### Architectures

These instructions are available in all T variants of the ARM architecture.

#### Examples

```    ASR r3,r5
LSR r0,r2,#6
LSR r5,r5,av    ; av must evaluate, at assembly time, to an
; integer in the range 1-32.
LSL r0,r4,#0    ; same as MOV r0,r4 except that C and V
; flags are not affected
```

#### Incorrect examples

```    ROR r2,r7,#3    ; ROR cannot use immediate shift value
LSL r9,r1       ; high registers not allowed
LSL r0,r7,#32   ; immediate shift out of range
ASR r0,r7,#0    ; immediate shift out of range
```