Chapter 5. Thumb Instruction Reference

This chapter describes the Thumb instructions that are provided by the ARM assembler and the inline assemblers in the ARM C and C++ compilers. It contains the following sections:

See Table 5.1 to locate individual directives or pseudo-instructions.

Table 5.1. Location of Thumb instructions and pseudo-instructions

Instruction mnemonicBrief descriptionPageArchitecture[1]
ADCAdd with carryADC, SBC, and MUL4T
ADDAddThumb arithmetic instructions4T
ADRLoad address (pseudo-instruction)ADR Thumb pseudo-instruction-
ANDLogical ANDAND, ORR, EOR, and BIC4T
ASRArithmetic shift rightASR, LSL, LSR, and ROR4T
BBranchB4T
BICBit clearAND, ORR, EOR, and BIC4T
BKPTBreakpointBKPT5T
BLBranch with linkBL4T
BLXBranch with link and exchange instruction setsBLX5T
BXBranch and exchange instruction setsBX4T
CMN, CMPCompare negative, Compare CMP and CMN4T
EORLogical exclusive ORAND, ORR, EOR, and BIC4T
LDMIALoad multiple registers, increment afterLDMIA and STMIA4T
LDRLoad register, immediate offsetLDR and STR, immediate offset4T
LDRLoad register, register offsetLDR and STR, register offset4T
LDRLoad register, pc or sp relativeLDR and STR, pc or sp relative4T
LDRLoad register (pseudo-instruction)LDR Thumb pseudo-instruction-
LSL, LSRLogical shift left, Logical shift rightASR, LSL, LSR, and ROR4T
MOVMoveMOV, MVN, and NEG4T
MULMultiplyADC, SBC, and MUL4T
MVN, NEGMove NOT, NegateMOV, MVN, and NEG4T
NOPNo operation (pseudo-instruction)NOP Thumb pseudo-instruction-
ORRLogical ORAND, ORR, EOR, and BIC4T
POP, PUSHPop registers from stack, Push registers onto stackPUSH and POP4T
RORRotate rightASR, LSL, LSR, and ROR4T
SBCSubtract with carryADC, SBC, and MUL4T
STMIAStore multiple registers, increment afterLDMIA and STMIA4T
STRStore register, immediate offsetLDR and STR, immediate offset4T
STRStore register, register offsetLDR and STR, register offset4T
STRStore register, pc or sp relativeLDR and STR, pc or sp relative4T
SUBSubtractThumb arithmetic instructions4T
SWISoftware interruptSWI4T
TSTTest bitsTST4T

[1] nT : available in T variants of ARM architecture version n and above

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