4.4.6. SMLAWy

Signed multiply-accumulate (32-bit by 16-bit, top 32-bit accumulate).

Syntax

SMLAW<y>{cond} Rd, Rm, Rs, Rn

where:

<y>

is either B or T. B meansuse the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs.

cond

is an optional condition code (see Conditional execution).

Rd

is the ARM register for the result.

Rm, Rs

are the ARM registers holding the values to be multiplied.

Rn

is the ARM register holding the value to be added.

r15 cannot be used for any of Rd, Rm, Rs, or Rn.

Any combination of Rd, Rm, Rs, and Rn can use the same registers.

Usage

The SMLAWy instruction multiplies the signed integer from the selected half of Rs by the signed integer from Rm, adds the 32-bit result to the 32-bit value in Rn, and places the result in Rd.

Condition flags

This instruction does not affect the N, Z, C or V flags.

If overflow occurs in the accumulation, it sets the Q flag. To read the state of the Q flag, use an MRS instruction (see MRS).

Note

This instruction never clears the Q flag. To clear the Q flag, use an MSR instruction (see MSR).

Architectures

This instruction is available in all E variants of ARM architecture v5 and above.

Examples

    SMLAWB      r2,r4,r7,r1
    SMLAWTVS    r0,r0,r9,r2

Incorrect examples

    SMLAWT      r15,r9,r3,r1    ; use of r15 not allowed
    SMLAWBS     r0,r4,r5,r1     ; use of S suffix not allowed
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