4.4.3. SMULxy

Signed multiply (16-bit by 16-bit, 32-bit result).

Syntax

SMUL<x><y>{cond} Rd, Rm, Rs

where:

<x>

is either B or T. B meansuse the bottom end (bits [15:0]) of Rm, T means use the top end (bits [31:16]) of Rm.

<y>

is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs.

cond

is an optional condition code (see Conditional execution).

Rd

is the ARM register for the result.

Rm, Rs

are the ARM registers holding the values to be multiplied.

r15 cannot be used for any of Rd, Rm, or Rs.

Any combination of Rd, Rm, and Rs can use the same registers.

Usage

The SMULxy instruction multiplies the 16-bit signed integers from the selected halves of Rm and Rs, and places the 32-bit result in Rd.

Condition flags

This instruction does not affect any flags.

Architectures

This instruction is available in all E variants of ARM architecture v5 and above.

Example

    SMULTBEQ      r8,r7,r9

Incorrect examples

    SMULBT      r15,r2,r0   ; use of r15 not allowed
    SMULTTS     r0,r6,r2    ; use of S suffix not allowed
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