4.4.4. SMLAxy

Signed multiply-accumulate (16-bit by 16-bit, 32-bit accumulate).


SMLA<x><y>{cond} Rd, Rm, Rs, Rn



is either B or T. B meansuse the bottom end (bits [15:0]) of Rm, T means use the top end (bits [31:16]) of Rm.


is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs.


is an optional condition code (see Conditional execution).


is the ARM register for the result.

Rm, Rs

are the ARM registers holding the values to be multiplied.


is the ARM register holding the value to be added.

r15 cannot be used for any of Rd, Rm, Rs, or Rn.

Any combination of Rd, Rm, Rs, and Rn can use the same registers.


The SMLAxy instruction multiplies the 16-bit signed integers from the selected halves of Rm and Rs, adds the 32-bit result to the 32-bit value in Rn, and places the result in Rd.

Condition flags

This instruction does not affect the N, Z, C, or V flags.

If overflow occurs in the accumulation, it sets the Q flag. To read the state of the Q flag, use an MRS instruction (see MRS).


This instruction never clears the Q flag. To clear the Q flag, use an MSR instruction (see MSR).


This instruction is available in all E variants of ARM architecture v5 and above.


    SMLATT      r8,r1,r0,r8
    SMLABBNE    r0,r2,r1,r10
    SMLABT      r0,r0,r3,r5

Incorrect examples

    SMLATB      r0,r7,r8,r15    ; use of r15 not allowed
    SMLATTS     r0,r6,r2        ; use of S suffix not allowed
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