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Home > ARM Instruction Reference > ARM general data processing instructions > Flexible second operand |

Most ARM general data processing instructions have a flexible
second operand. This is shown as in
the descriptions of the syntax of each instruction.

has
two possible forms:

#`immed_8r`

{,`Rm`

}`shift`

where:

`immed_8r`

is an expression evaluating to a numeric constant.The constant must correspond to an 8-bit pattern rotated by an even number of bits within a 32-bit word (but see

*Instruction substitution*).`Rm`

is the ARM register holding the data for the second operand. The bit pattern in the register can be shifted or rotated in various ways.

`shift`

is an optional shift to be applied to

. It can be any one of:`Rm`

`ASR`

`n`

arithmetic shift right

bits. 1 =`n`

= 32.`n`

`LSL`

`n`

logical shift left

bits. 0 =`n`

= 31.`n`

`LSR`

`n`

logical shift right

bits. 1 =`n`

= 32.`n`

`ROR`

`n`

rotate right

bits. 1 =`n`

= 31.`n`

`RRX`

rotate right one bit, with extend.

`type`

`Rs`

where:

`type`

is one of

`ASR`

,`LSL`

,`LSR`

,`ROR`

.`Rs`

is an ARM register supplying the shift amount. Only the least significant byte is used.

### Note

The result of the shift operation is used as

in the instruction, but`Operand2`

itself is not altered.`Rm`

Arithmetic shift right by bits
divides the value contained in

`Rm`

`n`

Logical shift right by bits
divides the value contained in

`Rm`

`n`

bits
of the register are set to 0.Logical shift left by bits
multiplies the value contained in

`Rm`

`n`

bits
of the register are set to 0.Rotate right by

bits
moves the right-hand n bits of the register into the left-hand `n`

bits of
the result. At the same time, all other bits are moved right by `n`

bits
(see Figure 4.1).`n`

Rotate right with extend shifts the contents of right
by one bit. The carry flag is copied into bit[31] of

`Rm`

The old value of bit[0] of is
shifted out to the carry flag if the

`S`

The carry flag is updated to the last bit shifted out of ,
if the instruction is any one of the following:

`MOV`

,`MVN`

,`AND`

,`ORR`

,`EOR`

or`BIC`

, if you use the`S`

suffix`TEQ`

or`TST`

, for which no`S`

suffix is required.

Certain pairs of instructions (`ADD`

and `SUB`

, `ADC`

and `SBC`

, `AND`

and `BIC`

, `MOV`

and `MVN`

, `CMP`

and `CMN`

)
are equivalent except for the negation or logical inversion of .

If a value of cannot
be expressed as a rotated 8-bit pattern, but its logical inverse
or negation could be, the assembler substitutes the other instruction
of the pair and inverts or negates

`immed_8r`

Be aware of this when comparing disassembly listings with source code.

ADD r3,r7,#1020 ; immed_8r. 1020 is 0xFF rotated right by 30 bits. AND r0,r5,r2 ; r2 contains the data for Operand2. SUB r11,r12,r3,ASR #5 ; Operand2 is the contents of r3 divided by 32. MOVS r4,r4, LSR #32 ; Updates the C flag to r4 bit 31. Clears r4 to 0.