4.4.2. UMULL, UMLAL, SMULL and SMLAL

Unsigned and signed long multiply and multiply accumulate (32-bit by 32-bit, 64-bit accumulate or result).

Syntax

Op{cond}{S} RdLo, RdHi, Rm, Rs

where:

Op

is one of UMULL, UMLAL, SMULL,or SMLAL.

cond

is an optional condition code (see Conditional execution).

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

RdLo, RdHi

are ARM registers for the result. For UMLAL and SMLAL they also hold the accumulating value.

Rm, Rs

are ARM registers holding the operands.

r15 cannot be used for any of RdHi, RdLo, Rm, or Rs.

RdLo, RdHi, and Rm must all be different registers.

Usage

The UMULL instruction interprets the values from Rm and Rs as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

The UMLAL instruction interprets the values from Rm and Rs as unsigned integers. It multiplies these integers, and adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.

The SMULL instruction interprets the values from Rm and Rs as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

The SMLAL instruction interprets the values from Rm and Rs as two’s complement signed integers. It multiplies these integers, and adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo.

Condition flags

If S is specified, these instructions:

  • update the N and Z flags according to the result

  • corrupt the C and V flags in ARM architecture v4 and earlier

  • do not affect the C or V flags in ARM architecture v5 and later.

Architectures

These instructions are available in ARM architecture v3M, and ARM architecture v4 and above except xM variants.

Examples

    UMULL       r0,r4,r5,r6
    UMLALS      r4,r5,r3,r8
    SMLALLES    r8,r9,r7,r6
    SMULLNE     r0,r1,r9,r0 ; Rs can be the same as other
                            ; registers

Incorrect examples

    UMULL       r1,r15,r10,r2   ; use of r15 not allowed
    SMULLLE     r0,r1,r0,r5     ; RdLo, RdHi and Rm must all be
                                ; different registers
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