4.2.4. LDM and STM

Load and store multiple registers. Any combination of registers r0 to r15 can be transferred.

Syntax

op{cond}mode Rn{!}, reglist{^}

where:

op

is either LDM or STM.

cond

is an optional condition code (see Conditional execution).

mode

is any one of the following:

IA

increment address after each transfer

IB

increment address before each transfer

DA

decrement address after each transfer

DB

decrement address before each transfer

FD

full descending stack

ED

empty descending stack

FA

full ascending stack

EA

empty ascending stack.

Rn

is the base register, the ARMregister containing the initial address for the transfer. Rn must not be r15.

!

is an optional suffix. If ! is present, the final address is written back into Rn.

reglist

is a list of registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range (see Examples).

^

is an optional suffix. You must not use it in User mode or System mode. It has two purposes:

  • If op is LDM and reglist contains the pc (r15), in addition to the normal multiple register transfer, the SPSR is copied into the CPSR. This is for returning from exception handlers. Use this only from exception modes.

  • Otherwise, data is transferred into or out of the User mode registers instead of the current mode registers.

Non word-aligned addresses

These instructions ignore bits [1:0] of the address. (On a system with a system coprocessor, if alignment checking is enabled, nonzero values in these bits cause an alignment exception.)

Loading to r15

A load to r15 (the program counter) causes a branch to the instruction at the address loaded. In T variants of ARM architecture v5 and above, a load to r15 causes a change to executing Thumb instructions if bit 0 of the value loaded is set.

Loading or storing the base register, with writeback

If Rn is in reglist, and writeback is specified with the ! suffix:

  • if op is STM and Rn is the lowest-numbered register in reglist, the initial value of Rn is stored

  • otherwise, the loaded or stored value of Rn is unpredictable.

Architectures

These instructions are available in all versions of the ARM architecture.

In T variants of ARM architecture v5 and above, a load to r15 causes a change to executing Thumb instructions if bit 0 of the value loaded is set.

Examples

    LDMIA   r8,{r0,r2,r9}
    STMDB   r1!,{r3-r6,r11,r12}
    STMFD   r13!,{r0,r4-r7,LR}  ; Push registers including the
                                ; stack pointer
    LDMFD   r13!,{r0,r4-r7,PC}  ; Pop the same registers and
                                ; return from subroutine

Incorrect examples

    STMIA   r5!,{r5,r4,r9} ; value stored for r5 unpredictable 
    LDMDA   r2, {}         ; must be at least one register in list
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