4.3.2. ADD, SUB, RSB, ADC, SBC, and RSC

Add, subtract, and reverse subtract, each with or without carry.

Syntax

op{cond}{S} Rd, Rn, Operand2

where:

op

is one of ADD, SUB, RSB, ADC, SBC,or RSC.

cond

is an optional condition code (see Conditional execution).

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

Rd

is the ARM register for the result.

Rn

is the ARM register holding the first operand.

Operand2

is a flexible second operand. See Flexible second operand for details of the options.

Usage

The ADD instruction adds the values in Rn and Operand2.

The SUB instruction subtracts the value of Operand2 from the value in Rn.

The RSB (Reverse SuBtract) instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2.

ADC, SBC, and RSC are used to synthesize multiword arithmetic (see Multiword arithmetic examples).

The ADC (ADd with Carry) instruction adds the values in Rn and Operand2, together with the carry flag.

The SBC (SuBtract with Carry) instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one.

The RSC (Reverse Subtract with Carry) instruction subtracts the value in Rn from the value of Operand2. If the carry flag is clear, the result is reduced by one.

In certain circumstances, the assembler can substitute one instruction for another. Be aware of this when reading disassembly listings. See Instruction substitution for details.

Condition flags

If S is specified, these instructions update the N, Z, C and V flags according to the result.

Use of r15

If you use r15 as Rn, the value used is the address of the instruction plus 8.

If you use r15 as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions (see the Handling Processor Exceptions chapter in ADS Developer Guide).

Caution

Do not use the S suffix when using r15 as Rd in User mode or System mode. The effect of such an instruction is unpredictable, but the assembler cannot warn you at assembly time.

You cannot use r15 for Rd or any operand in any data processing instruction that has a register-controlled shift (see Flexible second operand).

Architectures

These instructions are available in all versions of the ARM architecture.

Examples

    ADD     r2,r1,r3
    SUBS    r8,r6,#240      ; sets the flags on the result
    RSB     r4,r4,#1280     ; subtracts contents of r4 from 1280
    ADCHI   r11,r0,r3       ; only executed if C flag set and Z
                            ; flag clear
    RSCLES  r0,r5,r0,LSL r4 ; conditional, flags set

Incorrect example

    RSCLES  r0,r15,r0,LSL r4    ; r15 not allowed with register
                                ; controlled shift

Multiword arithmetic examples

These two instructions add a 64-bit integer contained in r2 and r3 to another 64-bit integer contained in r0 and r1, and place the result in r4 and r5.

    ADDS    r4,r0,r2    ; adding the least significant words
    ADC     r5,r1,r3    ; adding the most significant words

These instructions subtract one 96-bit integer from another:

    SUBS    r3,r6,r9
    SBCS    r4,r7,r10
    SBC     r5,r8,r11

For clarity, the above examples use consecutive registers for multiword values. There is no requirement to do this. The following, for example, is perfectly valid:

    SUBS    r6,r6,r9
    SBCS    r9,r2,r1
    SBC     r2,r8,r11
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