4.3.3. AND, ORR, EOR, and BIC

Logical AND, OR, Exclusive OR and Bit Clear.

Syntax

op{cond}{S} Rd, Rn, Operand2

where:

op

is one of AND, ORR, EOR,or BIC.

cond

is an optional condition code (see Conditional execution).

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

Rd

is the ARM register for the result.

Rn

is the ARM register holding the first operand.

Operand2

is a flexible second operand. See Flexible second operand for details of the options.

Usage

The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2.

The BIC (BIt Clear) instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2.

In certain circumstances, the assembler can substitute BIC for AND, or AND for BIC. Be aware of this when reading disassembly listings. See Instruction substitution for details.

Condition flags

If S is specified, these instructions:

  • update the N and Z flags according to the result

  • can update the C flag during the calculation of Operand2 (see Flexible second operand)

  • do not affect the V flag.

Use of r15

If you use r15 as Rn, the value used is the address of the instruction plus 8.

If you use r15 as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions (see the Handling Processor Exceptions chapter in ADS Developer Guide).

Caution

Do not use the S suffix when using r15 as Rd in User mode or System mode. The effect of such an instruction is unpredictable, but the assembler cannot warn you at assembly time.

You cannot use r15 for Rd or any operand in any data processing instruction that has a register-controlled shift (see Flexible second operand).

Architectures

These instructions are available in all versions of the ARM architecture.

Examples

    AND     r9,r2,#0xFF00
    ORREQ   r2,r0,r5
    EORS    r0,r0,r3,ROR r6
    BICNES  r8,r10,r0,RRX

Incorrect example

    EORS    r0,r15,r3,ROR r6    ; r15 not allowed with register
                                ; controlled shift
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