4.4.7. SMLALxy

Signed multiply-accumulate (16-bit by 16-bit, 64-bit accumulate).

Syntax

SMLAL<x><y>{cond} RdLo, RdHi, Rm, Rs

where:

<x>

is either B or T. B meansuse the bottom end (bits [15:0]) of Rm, T means use the top end (bits [31:16]) of Rm.

<y>

is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs.

cond

is an optional condition code (see Conditional execution).

RdHi, RdLo

are the ARM registers for the result. They also hold the add-in value.

Rm, Rs

are the ARM registers holding the values to be multiplied.

r15 cannot be used for any of RdHi, RdLo, Rm, or Rs.

Any combination of RdHi, RdLo, Rm, or Rs can use the same registers.

Usage

The SMLALxy instruction multiplies the signed integer from the selected half of Rs by the signed integer from the selected half of Rm, and adds the 32-bit result to the 64-bit value in RdHi and RdLo.

Condition flags

This instruction does not affect any flags.

Note

This instruction cannot raise an exception. If overflow occurs on this instruction, the result wraps round without any warning.

Architectures

This instruction is available in all E variants of ARM architecture v5 and above.

Examples

    SMLALTB     r2,r3,r7,r1
    SMLALBTVS   r0,r1,r9,r2

Incorrect examples

    SMLALTT     r8,r9,r3,r15    ; use of r15 not allowed
    SMLALBBS    r0,r1,r5,r2     ; use of S suffix not allowed
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