Chapter 4. ARM Instruction Reference

This chapter describes the ARM instructions that are supported by the ARM assembler. It contains the following sections:

See to Table 4.1 to locate individual instructions. Pseudo-instructions are listed on ARM pseudo-instructions.

Table 4.1. Location of ARM instructions

MnemonicBrief descriptionPageArchitecture[1]
ADC, ADDAdd with carry, AddADD, SUB, RSB, ADC, SBC, and RSCAll
ANDLogical ANDAND, ORR, EOR, and BICAll
BBranchB and BLAll
BICBit clearAND, ORR, EOR, and BICAll
BKPTBreakpointBKPT5
BLBranch with linkB and BLAll
BLXBranch, link and exchangeBLX5T[2]
BXBranch and exchangeBX4Tb
CDP, CDP2Coprocessor data operationCDP, CDP22, 5
CLZCount leading zeroesCLZ5
CMN, CMPCompare negative, CompareCMP and CMNAll
EORExclusive ORAND, ORR, EOR, and BICAll
LDC, LDC2Load coprocessorLDC, STC2, 5
LDMLoad multiple registersLDM and STMAll
LDRLoad registerARM memory access instructionsAll
MARMove from registers to 40-bit accumulatorMAR, MRAXScale[3]
MCR, MCR2, MCRRMove from register(s) to coprocessorMCR, MCR2, MCRR2, 5, 5E[4]
MIA, MIAPH, MIAxyMultiply with internal 40-bit accumulateMIA, MIAPH, and MIAxyXScale
MLAMultiply accumulateMUL and MLA2
MOVMoveMOV and MVNAll
MRAMove from 40-bit accumulator to registersMAR, MRAXScale
MRC, MRC2Move from coprocessor to registerMRC, MRC22, 5
MRRCMove from coprocessor to 2 registersMRRC5Ed
MRSMove from PSR to registerMRS3
MSRMove from register to PSR MSR3
MULMultiplyMUL and MLA2
MVNMove notMOV and MVNAll
ORRLogical ORAND, ORR, EOR, and BICAll
PLDCache preloadPLD5Ed
QADD, QDADD, QDSUB, QSUBSaturating arithmeticQADD, QSUB, QDADD, and QDSUB5ExP[5]
RSB, RSC, SBCReverse sub, Reverse sub with carry, Sub with carryADD, SUB, RSB, ADC, SBC, and RSCAll
SMLALSigned multiply-accumulate (64 <= 32 x 32 + 64)UMULL, UMLAL, SMULL and SMLALM[6]
SMLALxySigned multiply-accumulate (64 <= 16 x 16 + 64)SMLALxy5ExPe
SMLAWySigned multiply-accumulate (32 <= 32 x 16 + 32)SMLAWy5ExPe
SMLAxySigned multiply-accumulate (32 <= 16 x 16 + 32)SMLAxy5ExPe
SMULLSigned multiply (64 <= 32 x 32)UMULL, UMLAL, SMULL and SMLALMf
SMULWySigned multiply (32 <= 32 x 16)SMULWy5ExPe
SMULxySigned multiply (32 <= 16 x 16)SMULxy5ExPe
STC, STC2Store coprocessorLDC, STC2, 5ExPe
STMStore multiple registersLDM and STMAll
STRStore registerARM memory access instructionsAll
SUBSubtractADD, SUB, RSB, ADC, SBC, and RSCAll
SWISoftware interruptSWIAll
SWPSwap registers and memorySWP3
TEQ, TSTTest equivalence, TestTST and TEQAll
UMLAL, UMULLUnsigned MLA, MUL (64 <= 32 x 32 (+ 64))UMULL, UMLAL, SMULL and SMLALMf

[1] n : available in ARM architecture version n and above

[2] nT : available in T variants of ARM architecture version n and above

[3] XScale: XScale coprocessor instructions

[4] nE : available in E variants of ARM architecture version n and above, except ExP variants

[5] nE : available in all E variants of ARM architecture version n and above, including ExP variants

[6] M : available in ARM architecture version 3M, and 4 and above, except xM versions

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