4.4.5. SMULWy

Signed multiply (32-bit by 16-bit, top 32-bit result).


SMULW<y>{cond} Rd, Rm, Rs



is either B or T. B meansuse the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs.


is an optional condition code (see Conditional execution).


is the ARM register for the result.

Rm, Rs

are the ARM registers holding the operands.

r15 cannot be used for any of Rd, Rm, or Rs.

Any combination of Rd, Rm, and Rs can use the same registers.


The SMULWy instruction multiplies the signed integer from the selected half of Rs by the signed integer from Rm, and places the upper 32-bits of the 48-bit result in Rd.

Condition flags

This instruction does not affect any flags.


This instruction is available in all E variants of ARM architecture v5 and above.


    SMULWB      r2,r4,r7
    SMULWTVS    r0,r0,r9

Incorrect examples

    SMULWT      r15,r9,r3   ; use of r15 not allowed
    SMULWBS     r0,r4,r5    ; use of S suffix not allowed
Copyright © 2000, 2001 ARM Limited. All rights reserved.ARM DUI 0068B