4.4.8. MIA, MIAPH, and MIAxy

XScale coprocessor 0 instructions.

Multiply with internal accumulate (32-bit by 32-bit, 40-bit accumulate).

Multiply with internal accumulate, packed halfwords (16-bit by 16-bit twice, 40-bit accumulate).

Multiply with internal accumulate (16-bit by 16-bit, 40-bit accumulate).

Syntax

MIA{cond} Acc, Rm, Rs
MIAPH{cond} Acc, Rm, Rs
MIA<x><y>{cond} Acc, Rm, Rs

where:

cond

is an optional condition code (see Conditional execution).

Acc

is the internal accumulator. The standard name is accx, where x is an integer in the range 0-n. The value of n depends on the processor. It is 0 in current processors.

Rm, Rs

are the ARM registers holding the values to be multiplied.

<x>

is either B or T. B means use the bottom end (bits [15:0]) of Rm, T means use the top end (bits [31:16]) of Rm.

<y>

is either B or T. B means use the bottom end (bits [15:0]) of Rs, T means use the top end (bits [31:16]) of Rs.

r15 cannot be used for either Rm or Rs.

Usage

The MIA instruction multiplies the signed integers from Rs and Rm, and adds the result to the 40-bit value in Acc.

The MIAPH instruction multiplies the signed integers from the lower halves of Rs and Rm, multiplies the signed integers from the upper halves of Rs and Rm, and adds the two 32-bit results to the 40-bit value in Acc.

The MIAxy instruction multiplies the signed integer from the selected half of Rs by the signed integer from the selected half of Rm, and adds the 32-bit result to the 40-bit value in Acc.

Condition flags

These instructions do not affect any flags.

Note

These instructions cannot raise an exception. If overflow occurs on these instructions, the result wraps round without any warning.

Architectures

These instructions are only available in XScale.

Examples

    MIA     acc0,r5,r0
    MIALE   acc0,r1,r9
    MIAPH   acc0,r0,r7
    MIAPHNE acc0,r11,r10
    MIABB   acc0,r8,r9
    MIABT   acc0,r8,r8
    MIATB   acc0,r5,r3
    MIATT   acc0,r0,r6
    MIABTGT acc0,r2,r5
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